Imaging device and electronic device

ABSTRACT

Regarding a column signal processing system including a successive approximation register analog-to-digital converter, an imaging device capable of operating at further higher speed and with further lower power consumption is provided. An imaging device of the present disclosure is provided with a pixel array unit including a plurality of pixels each including a photoelectric conversion element, a column amplifier unit that obtains a difference between a reset component and a signal component input from each pixel of the pixel array unit via a signal line, and outputs the difference as a pixel signal, a capacitance unit that holds the pixel signal input from the column amplifier unit, and a successive approximation register analog-to-digital conversion unit that converts an analog pixel signal input from the capacitance unit into a digital signal, in which the capacitance unit differentiates a single-phase pixel signal input from the column amplifier unit using a reference voltage that defines a zero voltage of the pixel signal.

TECHNICAL FIELD

The present disclosure relates to an imaging device and an electronicdevice.

BACKGROUND ART

An analog-to-digital converter that converts an analog signal (pixelsignal) output from a pixel into a digital signal is mounted on animaging device, and a successive approximation register (SAR)analog-to-digital converter is used as the analog-to-digital converter(refer to, for example, Patent Document 1).

CITATION LIST Patent Document

-   Patent Document 1: Japanese Patent Application Laid-Open No.    2019-092143

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

A successive approximation register analog-to-digital converter isexcellent in that an operation at higher speed and with lower powerconsumption as compared with that of a so-called single-slopeanalog-to-digital converter is possible. A column signal processingsystem including this successive approximation registeranalog-to-digital converter is desired to operate at further higherspeed and with further lower power consumption.

Therefore, an object of the present disclosure is to provide an imagingdevice capable of operating at further higher speed and with furtherlower power and an electronic device including the imaging deviceregarding the column signal processing system including the successiveapproximation register analog-to-digital converter.

Solutions to Problems

According to the present disclosure, provided is an imaging deviceprovided with:

a pixel array unit including a plurality of pixels each including aphotoelectric conversion element;

a column amplifier unit that obtains a difference between a resetcomponent and a signal component input from each pixel of the pixelarray unit via a signal line, and outputs the difference as a pixelsignal;

a capacitance unit that holds the pixel signal input from the columnamplifier unit; and

a successive approximation register analog-to-digital conversion unitthat converts an analog pixel signal input from the capacitance unitinto a digital signal, in which the capacitance unit differentiates asingle-phase pixel signal input from the column amplifier unit using areference voltage that defines a zero voltage of the pixel signal.

The column amplifier unit may include: an amplifier to a non-invertinginput terminal of which a potential of the signal line is input;

a first switch one end of which is connected to an output terminal ofthe amplifier and another end of which is connected to an invertinginput terminal of the amplifier;

a second switch one end of which is connected to the output terminal ofthe amplifier;

a first capacitance element one end of which is connected to another endof the second switch and another end of which is connected to theanother end of the first switch and the inverting input terminal of theamplifier;

a second capacitance element connected between the another end of thefirst capacitance element and the inverting input terminal of theamplifier, and a reference potential node; and a third switch one end ofwhich is connected to the another end of the second switch and one endof the first capacitance element, the third switch to another end ofwhich the reference voltage is applied.

The column amplifier unit may put the first switch into a closed stateand charge the first capacitance element and the second capacitanceelement with the reset component when the reset component is input, andput the third switch into a closed state and apply the reference voltageto the another end of the second switch and the one end of the firstcapacitance element, then, put the first switch and the third switchinto an opened state and put the second switch into a closed state, andform a non-inverting amplification circuit using the first capacitanceelement, the second capacitance element, and the amplifier, and

feed back so that a voltage of a common connection node of the firstcapacitance element and the second capacitance element becomes a samevoltage as the signal component when the signal component is input.

The Capacitance Unit

may have a configuration of a differential circuit including apositive-side capacitance element charged with the pixel signal inputfrom the column amplifier unit, and a negative-side capacitance elementcharged with the reference voltage, and

include a fourth switch that selectively short-circuits input ends ofthe positive-side capacitance element and the negative-side capacitanceelement.

The fourth switch may short-circuit the input ends of the positive-sidecapacitance element and the negative-side capacitance element when thepixel signal with which the positive-side capacitance element is chargedand the reference voltage with which the negative-side capacitanceelement is charged are transmitted to the successive approximationregister analog-to-digital conversion unit.

The capacitance unit may hold the pixel signal input from the columnamplifier unit by sampling by a switched capacitor.

It is possible to multiplex and process each potential of a plurality ofsignal lines via a plurality of column amplifiers and capacitance unitscorresponding to the plurality of signal lines for one successiveapproximation register analog-to-digital converter of the successiveapproximation register analog-to-digital conversion unit.

The capacitance unit may be provided with:

a first node to which the pixel signal input from the column amplifierunit is supplied;

a second node to which the reference voltage is supplied;

a positive-side capacitance element and a negative-side capacitanceelement connected in series between the first node and the second node;

a fourth switch that selectively short-circuits the first node and thesecond node;

a fifth switch that selectively applies a common mode reference voltageof the successive approximation register analog-to-digital conversionunit to a common connection node of the positive-side capacitanceelement and the negative-side capacitance element;

a sixth switch that selectively connects the second node and a firstinput end of the successive approximation register analog-to-digitalconversion unit; and

a seventh switch that selectively connects the first node and a secondinput end of the successive approximation register analog-to-digitalconversion unit.

The fourth switch may be temporarily put into a closed state immediatelybefore the capacitance unit starts holding the pixel signal, andshort-circuit input ends of the positive-side capacitance element andthe negative-side capacitance element, and

the fifth switch may be temporarily put into a closed state immediatelybefore the capacitance unit starts holding the pixel signal and in aperiod in which the pixel signal held by the capacitance unit istransferred to the successive approximation register analog-to-digitalconversion unit, and apply the common mode reference voltage of thesuccessive approximation register analog-to-digital conversion unit tothe common connection node of the positive-side capacitance element andthe negative-side capacitance element.

The capacitance unit may be provided with:

a first node to which the pixel signal input from the column amplifierunit is supplied;

a second node to which the reference voltage is supplied;

a positive-side capacitance element and a negative-side capacitanceelement connectable in series between the first node and the secondnode;

a 4a switch and a 4b switch connected in series between the first nodeand the second node;

a 5a switch, the positive-side capacitance element, the negative-sidecapacitance element, and a 5b switch connected in series between thefirst node and the second node;

a 5c switch that selectively applies a common mode reference voltage ofthe successive approximation register analog-to-digital conversion unitto a common connection node of the positive-side capacitance element andthe negative-side capacitance element;

a sixth switch that selectively connects the second node and a firstinput end of the successive approximation register analog-to-digitalconversion unit; and

a seventh switch that selectively connects the first node and a secondinput end of the successive approximation register analog-to-digitalconversion unit.

The 4a switch and the 4b switch may be temporarily put into a closedstate immediately before the capacitance unit starts holding the pixelsignal and immediately before the pixel signal held by the capacitanceunit is transferred to the successive approximation registeranalog-to-digital conversion unit, and apply the common mode referencevoltage of the successive approximation register analog-to-digitalconversion unit to the first node and the second node,

the 5a switch and the 5b switch may be temporarily put into an openedstate immediately before the pixel signal held by the capacitance unitis transferred to the successive approximation registeranalog-to-digital conversion unit, and block the connection between thefirst node and the positive-side capacitance element and block theconnection between the second node and the negative-side capacitanceelement, and

the 5c switch may be temporarily put into a closed state immediatelybefore the capacitance unit starts holding the pixel signal and in aperiod in which the pixel signal held by the capacitance unit istransferred to the successive approximation register analog-to-digitalconversion unit, and apply the common mode reference voltage of thesuccessive approximation register analog-to-digital conversion unit tothe common connection node of the positive-side capacitance element andthe negative-side capacitance element.

The capacitance unit may be provided with:

a first node to which the pixel signal input from the column amplifierunit is supplied;

a second node to which the reference voltage is supplied;

a 4a switch and a 4b switch connected in series between the first nodeand the second node;

a positive-side capacitance element, a 5a switch, a 5b switch, and anegative-side capacitance element connected in series between the firstnode and the second node;

a 5c switch that selectively applies a common mode reference voltage ofthe successive approximation register analog-to-digital conversion unitto a common connection node of the 5a switch and the 5b switch;

a sixth switch that selectively connects the second node and a firstinput end of the successive approximation register analog-to-digitalconversion unit; and

a seventh switch that selectively connects the first node and a secondinput end of the successive approximation register analog-to-digitalconversion unit.

The 4a switch and the 4b switch may be temporarily put into a closedstate immediately before the capacitance unit starts holding the pixelsignal and immediately before the pixel signal held by the capacitanceunit is transferred to the successive approximation registeranalog-to-digital conversion unit, and apply the common mode referencevoltage of the successive approximation register analog-to-digitalconversion unit to the first node and the second node,

the 5c switch may be temporarily put into a closed state immediatelybefore the capacitance unit starts holding the pixel signal and in aperiod in which the pixel signal held by the capacitance unit istransferred to the successive approximation register analog-to-digitalconversion unit, and apply the common mode reference voltage of thesuccessive approximation register analog-to-digital conversion unit to acommon connection node of the positive-side capacitance element and thenegative-side capacitance element, and

the 5a switch and the 5b switch may be temporarily put into an openedstate immediately before the pixel signal held by the capacitance unitis transferred to the successive approximation registeranalog-to-digital conversion unit, and block the connection between thepositive-side capacitance element and the negative-side capacitanceelement.

The capacitance unit may be provided with:

a first node to which the pixel signal input from the column amplifierunit is supplied;

a second node to which the reference voltage is supplied;

a positive-side capacitance element one end of which is connected to thefirst node;

a third node to which another end of the positive-side capacitanceelement is connected;

a negative-side capacitance element one end of which is connected to thesecond node;

a fourth node to which another end of the negative-side capacitanceelement is connected;

a 4a switch and a 4b switch connected in series between the first nodeand the second node;

a 4c switch connected between the first node and the second node;

a 5a switch connected between the third node and the fourth node;

a 5b switch and a 5c switch connected in series between the third nodeand the fourth node;

a sixth switch that selectively connects the third node and a firstinput end of the successive approximation register analog-to-digitalconversion unit; and

a seventh switch that selectively connects the fourth node and a secondinput end of the successive approximation register analog-to-digitalconversion unit.

The 4a switch and the 4b switch may be temporarily put into a closedstate in a period in which the pixel signal held by the capacitance unitis transferred to the successive approximation registeranalog-to-digital conversion unit, and apply a common mode referencevoltage of the successive approximation register analog-to-digitalconversion unit to the first node and the second node,

the 4c switch may be put into a closed state immediately before thecapacitance unit starts holding the pixel signal, and short-circuit thefirst node and the second node,

the 5a switch may short-circuit the third node and the fourth node in aperiod in which the capacitance unit holds the pixel signal, and

the 5b switch and the 5c switch may be put into a closed stateimmediately before the capacitance unit starts holding the pixel signal,and apply the reference voltage to the third node and the fourth node.

The capacitance unit may be provided with:

a first node to which the pixel signal input from the column amplifierunit is supplied;

a second node to which the reference voltage is supplied;

a positive-side capacitance element one end of which is connected to thefirst node;

a third node to which another end of the positive-side capacitanceelement is connected;

a negative-side capacitance element one end of which is connected to thesecond node;

a fourth node to which another end of the negative-side capacitanceelement is connected;

a fourth switch connected between the first node and the second node;

a 5a switch and a 5b switch connected in series between the third nodeand the fourth node;

a 5c switch that selectively applies a common mode reference voltage ofthe successive approximation register analog-to-digital conversion unitto a common connection node of the 5a switch and the 5b switch;

a sixth switch that selectively connects the third node and a firstinput end of the successive approximation register analog-to-digitalconversion unit; and

a seventh switch that selectively connects the fourth node and a secondinput end of the successive approximation register analog-to-digitalconversion unit.

The fourth switch may be put into a closed state immediately before thecapacitance unit starts holding the pixel signal and in a period inwhich the pixel signal held by the capacitance unit is transferred tothe successive approximation register analog-to-digital conversion unit,and short-circuit the first node and the second node,

the 5a switch and the 5b switch may be put into a closed stateimmediately before a period in which the capacitance unit holds thepixel signal until the holding period ends, and short-circuit the thirdnode and the fourth node; and

the 5c switch may be put into a closed state immediately before thecapacitance unit starts holding the pixel signal, and selectively applythe common mode reference voltage of the successive approximationregister analog-to-digital conversion unit to the common connection nodeof the 5a switch and the 5b switch.

The capacitance unit may be provided with:

a first node to which the pixel signal input from the column amplifierunit is supplied;

a second node to which the reference voltage is supplied;

a positive-side capacitance element one end of which is connected to thefirst node;

a third node to which another end of the positive-side capacitanceelement is connected;

a negative-side capacitance element one end of which is connected to thesecond node;

a fourth node to which another end of the negative-side capacitanceelement is connected;

a 4a switch and a 4b switch connected in series between the first nodeand the second node;

a 4c switch that selectively applies the reference voltage to a commonconnection node of the 4a switch and the 4b switch;

a 5a switch and a 5b switch connected in series between the third nodeand the fourth node;

a 5c switch that selectively applies a common mode reference voltage ofthe successive approximation register analog-to-digital conversion unitto a common connection node of the 5a switch and the 5b switch;

a sixth switch that selectively connects the third node and a firstinput end of the successive approximation register analog-to-digitalconversion unit; and

a seventh switch that selectively connects the fourth node and a secondinput end of the successive approximation register analog-to-digitalconversion unit.

The 4a switch and the 4b switch may be temporarily put into a closedstate immediately before the capacitance unit starts holding the pixelsignal, immediately before a period in which the pixel signal held bythe capacitance unit is transferred to the successive approximationregister analog-to-digital conversion unit, and the transferring period,and short-circuit the first node and the second node,

the 4c switch may be temporarily put into a closed state immediatelybefore the capacitance unit starts holding the pixel signal andimmediately before a period in which the pixel signal held by thecapacitance unit is transferred to the successive approximation registeranalog-to-digital conversion unit, and apply the reference voltage tothe common connection node of the 4a switch and the 4b switch,

the 5a switch and the 5b switch may be temporarily put into a closedstate immediately before the capacitance unit starts holding the pixelsignal and in a period in which the capacitance unit holds the pixelsignal, and short-circuit the third node and the fourth node, and

the 5c switch may be temporarily put into a closed state immediatelybefore the capacitance unit starts holding the pixel signal, and applythe common mode reference voltage of the successive approximationregister analog-to-digital conversion unit to the common connection nodeof the 5a switch and the 5b switch.

According to the present disclosure, provided is an electronic deviceprovided with:

an imaging device that outputs a photoelectrically converted digitalsignal; and

a signal processing unit that performs signal processing on the basis ofthe digital signal, in which

the imaging device is provided with:

a pixel array unit including a plurality of pixels each including aphotoelectric conversion element;

a column amplifier unit that obtains a difference between a resetcomponent and a signal component input from each pixel of the pixelarray unit via a signal line, and outputs the difference as a pixelsignal;

a capacitance unit that holds the pixel signal input from the columnamplifier unit; and

a successive approximation register analog-to-digital conversion unitthat converts an analog signal input from the capacitance unit into adigital signal, and

the capacitance unit differentiates a single-phase pixel signal inputfrom the column amplifier unit using a reference voltage that defines azero voltage of the pixel signal.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram illustrating an outline of a basicconfiguration of a CMOS image sensor, which is an example of an imagingdevice to which the technology according to the present disclosure isapplied.

FIG. 2 is a circuit diagram illustrating an example of a circuitconfiguration of a pixel.

FIG. 3 is a plan view schematically illustrating an outline of a flatsemiconductor chip structure of the CMOS image sensor.

FIG. 4 is an exploded perspective view schematically illustrating anoutline of a stacked semiconductor chip structure of the CMOS imagesensor.

FIG. 5 is a block diagram illustrating an outline of a configuration ofa CMOS image sensor, which is an example of an imaging device accordingto a first embodiment of the present disclosure.

FIG. 6 is a circuit diagram illustrating an outline of a configurationof a column signal processing system according to the first embodiment.

FIG. 7 is a timing chart for explaining a circuit operation of thecolumn signal processing system according to the first embodiment.

FIG. 8 is a circuit diagram illustrating an outline of a configurationof a column signal processing system according to Example 2.

FIG. 9 is a diagram for explaining a level diagram.

FIG. 10 is a circuit diagram illustrating an example of a configurationof a current reuse column amplifier.

FIG. 11 is a detailed circuit diagram of a successive approximationregister analog-to-digital converter.

FIG. 12 is a circuit diagram illustrating an internal configuration of acapacitance unit according to a second embodiment.

FIG. 13 is a timing chart of the capacitance unit in FIG. 12 .

FIG. 14 is a diagram illustrating input signal dependency of adifferential signal transferred from the capacitance unit to asuccessive approximation register analog-to-digital converter in FIG. 12.

FIG. 15 is a circuit diagram illustrating an internal configuration of acapacitance unit according to a first variation of FIG. 12 .

FIG. 16 is a timing chart of the capacitance unit in FIG. 15 .

FIG. 17 is a diagram illustrating input signal dependency of adifferential signal transferred from the capacitance unit to asuccessive approximation register analog-to-digital converter in FIG. 15.

FIG. 18 is a circuit diagram illustrating an internal configuration of acapacitance unit according to a second variation of FIG. 12 .

FIG. 19 is a timing chart of the capacitance unit in FIG. 18 .

FIG. 20 is a diagram illustrating input signal dependency of adifferential signal transferred from the capacitance unit to asuccessive approximation register analog-to-digital converter in FIG. 18.

FIG. 21 is a circuit diagram illustrating an internal configuration of acapacitance unit according to a third variation of FIG. 12 .

FIG. 22 is a timing chart of the capacitance unit in FIG. 21 .

FIG. 23 is a diagram illustrating input signal dependency of adifferential signal transferred from the capacitance unit to asuccessive approximation register analog-to-digital converter in FIG. 21.

FIG. 24 is a circuit diagram illustrating an internal configuration of acapacitance unit according to a fourth variation of FIG. 12 .

FIG. 25 is a timing chart of the capacitance unit in FIG. 24 .

FIG. 26 is a diagram illustrating input signal dependency of adifferential signal transferred from the capacitance unit to asuccessive approximation register analog-to-digital converter in FIG. 24.

FIG. 27 is a circuit diagram illustrating an internal configuration of acapacitance unit according to a fifth variation of FIG. 12 .

FIG. 28 is a timing chart of the capacitance unit in FIG. 27 .

FIG. 29 is a diagram illustrating input signal dependency of adifferential signal transferred from the capacitance unit to asuccessive approximation register analog-to-digital converter in FIG. 27.

FIG. 30 is a block diagram illustrating an example of a systemconfiguration of an indirect TOF distance image sensor according to asecond embodiment of the present disclosure.

FIG. 31 is a circuit diagram illustrating an example of a circuitconfiguration of a pixel in the indirect TOF distance image sensoraccording to the second embodiment.

FIG. 32 is a diagram illustrating an application example of thetechnology according to the present disclosure.

FIG. 33 is a block diagram illustrating an outline of a configurationexample of an imaging system as an example of an electronic device ofthe present disclosure.

FIG. 34 is a block diagram depicting an example of schematicconfiguration of a vehicle control system as an example of a mobile bodycontrol system to which the technology according to an embodiment of thepresent disclosure can be applied.

FIG. 35 is a diagram depicting an example of an installation position ofan imaging section in the mobile body control system.

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a mode for carrying out the technology according to thepresent disclosure (hereinafter, referred to as an “embodiment”) isdescribed in detail with reference to the drawings. The technologyaccording to the present disclosure is not limited to the embodiment,and various numerical values in the embodiment are examples. In thefollowing description, the same reference sign is used for the sameelements or elements having the same function, and the description isnot repeated. Note that, the description is given in the followingorder.

1. Description regarding Imaging Device and Electronic Device of PresentDisclosure in General

2. Imaging Device to Which Technology according to Present Disclosure IsApplied

2-1. Configuration Example of CMOS Image Sensor

2-2. Circuit Configuration Example of Pixel

2-3. Semiconductor Chip Structure

2-3-1. Flat Semiconductor Chip Structure

2-3-2. Stacked Semiconductor Chip Structure

2-4. Regarding Single-Slope Analog-to-Digital Converter

3. First Embodiment of Present Disclosure (Example of CMOS Image Sensor)

3-1. First Embodiment (Example in Which Circuit Configuration ofCapacitance Unit and after This Is Made Configuration of DifferentialCircuit)

3-1-1. Configuration Example of Column Amplifier

3-1-2. Configuration Example of Capacitance Multiplexer

3-1-3. Configuration Example of Successive Approximation RegisterAnalog-to-Digital Converter

3-1-4. Circuit Operation of Column Signal Processing System

3-2. Example 2 (Implementation Example of Column Signal ProcessingSystem)

3-2-1. Power Supply Voltage and Used Transistor

3-2-2. Regarding Level Diagram

3-2-3. Regarding Timing

3-2-4. Configuration Example of Column Amplifier

3-2-5. Configuration Example of Successive Approximation RegisterAnalog-to-Digital Converter

4. Second Embodiment of Present Disclosure (Example of Indirect TOFDistance Image Sensor)

4-1. System Configuration Example

4-2. Circuit Configuration Example of Pixel

5. Variation

6. Application Example

7. Application Example of Technology according to Present Disclosure

7-1. Electronic Device of Present Disclosure (Example of Imaging Device)

7-2. Application Example to Mobile Body

8. Configuration that Present Disclosure may Take

<Description Regarding Imaging Device and Electronic Device of PresentDisclosure in General>

In an imaging device and an electronic device of the present disclosure,a column amplifier unit may include an amplifier to a non-invertinginput terminal of which a potential of a signal line is input, a firstswitch one end of which is connected to an output terminal of theamplifier and another end of which is connected to an inverting inputterminal of the amplifier, a second switch one end of which is connectedto the output terminal of the amplifier, a first capacitance element oneend of which is connected to another end of the second switch andanother end of which is connected to the another end of the first switchand the inverting input terminal of the amplifier, a second capacitanceelement connected between the another end of the first capacitanceelement and the inverting input terminal of the amplifier, and areference potential node, and a third switch one end of which isconnected to the another end of the second switch and one end of thefirst capacitance element, the third switch to another end of which thereference voltage is applied.

In the imaging device and the electronic device of the presentdisclosure including the preferred configuration described above, thecolumn amplifier unit may put the first switch into a closed state andcharge the first capacitance element and the second capacitance elementwith a reset component when the reset component is input, and put thethird switch into a closed state and take in the reference voltage,then, put the first switch and the third switch into an opened state andput the second switch into a closed state, and form a non-invertingamplification circuit using the first capacitance element, the secondcapacitance element, and the amplifier, and feed back so that a voltageof a common connection node of the first capacitance element and thesecond capacitance element becomes a same voltage as a signal componentwhen the signal component is input.

Furthermore, in the imaging device and the electronic device of thepresent disclosure including the preferred configuration describedabove, a capacitance unit may have a configuration of a differentialcircuit including a positive-side capacitance element charged with thepixel signal input from the column amplifier unit and a negative-sidecapacitance element charged with the reference voltage, and include aninter-differential short-circuit switch (fourth switch) that selectivelyshort-circuits input ends of the positive-side capacitance element andthe negative-side capacitance element.

Furthermore, in the imaging device and the electronic device of thepresent disclosure including the preferred configuration describedabove, the inter-differential short-circuit switch (fourth switch) mayshort-circuit the input ends of the positive-side capacitance elementand the negative-side capacitance element when the pixel signal withwhich the positive-side capacitance element is charged and the referencevoltage with which the negative-side capacitance element is charged aretransmitted to the successive approximation register analog-to-digitalconversion unit. Furthermore, the capacitance unit may hold the pixelsignal input from the column amplifier unit by sampling by a switchedcapacitor.

Furthermore, in the imaging device and the electronic device of thepresent disclosure including the preferred configuration describedabove, it is possible to multiplex and process each potential of aplurality of signal lines via a plurality of column amplifiers andcapacitance units corresponding to the plurality of signal lines for onesuccessive approximation register analog-to-digital converter of thesuccessive approximation register analog-to-digital conversion unit.

<Imaging Device to which Technology According to Present Disclosure isApplied>

First, a basic configuration of an imaging device to which thetechnology according to the present disclosure is applied is described.Here, a complementary metal oxide semiconductor (CMOS) image sensor,which is a type of an X-Y address system imaging device, is described asan example of the imaging device. The CMOS image sensor is an imagesensor fabricated by applying or partially using a CMOS process.

[Configuration Example of CMOS Image Sensor]

FIG. 1 is a block diagram illustrating an outline of a basicconfiguration of the CMOS image sensor, which is an example of theimaging device to which the technology according to the presentdisclosure is applied.

A CMOS image sensor 10 according to this example includes a pixel arrayunit 11 and a peripheral circuit unit of the pixel array unit 11. Thepixel array unit 11 is obtained by two-dimensionally arranging pixels(pixel circuits) 20 each including a photoelectric conversion element ina row direction and a column direction, that is, in a matrix. Here, therow direction refers to an array direction of the pixels 20 of a pixelrow, and the column direction refers to an array direction of the pixels20 of a pixel column. The pixel 20 performs photoelectric conversion togenerate a photocharge according to an amount of received light toaccumulate.

The peripheral circuit unit of the pixel array unit 11 includes, forexample, a row selection unit 12, a constant current source unit 13, acolumn amplifier unit 14, an analog-to-digital conversion unit 15, ahorizontal transfer scanning unit 16, a signal processing unit 17, atiming control unit 18 and the like.

In the pixel array unit 11, a pixel control line 31 (31 ₁ to 31 _(m)) iswired in the row direction for each pixel row for the matrix-shapedpixel array. Furthermore, a signal line 32 (32 ₁ to 32 _(n)) is wired inthe column direction for each pixel column. The pixel control line 31transmits a drive signal for driving when reading a signal from thepixel 20. In FIG. 1 , the pixel control line 31 is illustrated as onewire, but the number thereof is not limited to one. One end of the pixelcontrol line 31 is connected to an output end corresponding to each rowof the row selection unit 12.

Respective components of the peripheral circuit unit of the pixel arrayunit 11, that is, the row selection unit 12, the constant current sourceunit 13, the column amplifier unit 14, the analog-to-digital conversionunit 15, the horizontal transfer scanning unit 16, the signal processingunit 17, and the timing control unit 18 are hereinafter described.

The row selection unit 12 includes a shift register, an address decoderand the like, and controls scanning of the pixel row and an address ofthe pixel row when selecting each pixel 20 of the pixel array unit 11.Although a specific configuration of the row selection unit 12 is notillustrated, this generally includes two scanning systems, which are aread scanning system and a sweep scanning system.

The read scanning system sequentially selectively scans the pixels 20 inthe pixel array unit 11 in units of row in order to read a pixel signalfrom the pixel 20. The pixel signal read from the pixel 20 is an analogsignal. The sweep scanning system performs, on a read row on which theread scanning is performed by the read scanning system, sweep scanningprior to the read scanning by time corresponding to a shutter speed.

By the sweep scanning by the sweep scanning system, an unnecessarycharge is swept out of the photoelectric conversion element of the pixel20 of the read row, so that the photoelectric conversion element isreset. Then, a so-called electronic shutter operation is performed bysweeping the unnecessary charge (resetting) by the sweep scanningsystem. Here, the electronic shutter operation is intended to mean anoperation of discharging the photocharge of the photoelectric conversionelement and newly starting exposure (starting accumulating thephotocharge).

The constant current source unit 13 is provided with a plurality of loadcurrent sources I (refer to FIG. 2 ) each including, for example, a MOStransistor, connected to the signal lines 32 ₁ to 32 _(n), respectively,for respective pixel columns, and supplies a bias current to each pixel20 of the pixel row selectively scanned by the row selection unit 12 viaeach of the signal lines 32 ₁ to 32 _(n).

The column amplifier unit 14 includes a set of column amplifiersprovided corresponding to the signal lines 32 ₁ to 32 _(n),respectively, for respective pixel columns. Then, each column amplifierof the column amplifier unit 14 amplifies the pixel signal read fromeach pixel 20 of the pixel array unit 11 and supplied via each of thesignal lines 32 ₁ to 32 _(n), and supplies the same to theanalog-to-digital conversion unit 15.

The analog-to-digital conversion unit 15 is a column-parallelanalog-to-digital conversion unit including a set of a plurality ofanalog-to-digital converters provided corresponding to the pixel columnsof the pixel array unit 11, respectively (for example, provided for eachpixel column). The analog-to-digital conversion unit 15 converts ananalog pixel signal output via each of the signal lines 32 ₁ to 32 _(n)for each pixel column and amplified by the column amplifier unit 14 intoa digital pixel signal.

The horizontal transfer scanning unit 16 includes a shift register, anaddress decoder and the like, and controls scanning of the pixel columnand an address of the pixel column when reading the signal of each pixel20 of the pixel array unit 11. Under the control of the horizontaltransfer scanning unit 16, the pixel signals converted into the digitalsignals by the analog-to-digital conversion unit 15 are read to ahorizontal transfer line L in units of pixel column.

The signal processing unit 17 performs predetermined signal processingon the digital pixel signal supplied via the horizontal transfer line Lto generate two-dimensional image data. For example, the signalprocessing unit 17 performs digital signal processing such as correctionof a vertical line defect or a point defect, parallel-to-serialconversion, compression, encoding, addition, averaging, and anintermittent operation. The signal processing unit 17 outputs thegenerated image data to a subsequent device as an output signal of thisCMOS image sensor 10.

The timing control unit 18 generates various timing signals, clocksignals, control signals and the like, and performs drive control of therow selection unit 12, the constant current source unit 13, the columnamplifier unit 14, the analog-to-digital conversion unit 15, thehorizontal transfer scanning unit 16, the signal processing unit 17 andthe like on the basis of the generated signals.

[Circuit Configuration Example of Pixel]

FIG. 2 is a circuit diagram illustrating an example of a configurationof the pixel (pixel circuit) 20. The pixel 20 includes, for example, aphotodiode 21 as the photoelectric conversion element. The pixel 20includes, in addition to the photodiode 21, a transfer transistor 22, areset transistor 23, an amplification transistor 24, and a selectiontransistor 25.

As the four transistors of the transfer transistor 22, the resettransistor 23, the amplification transistor 24, and the selectiontransistor 25, an N-channel MOS field effect transistor (FET) is used,for example. However, a combination of conductivity types of the fourtransistors 22 to 25 herein illustrated is merely an example, and thecombination is not limited thereto.

For the pixel 20, as the pixel control line 31 described above, aplurality of pixel control lines is wired in common to the respectivepixels 20 of the same pixel row. The plurality of pixel control lines isconnected to the output end corresponding to each pixel row of the rowselection unit 12 in units of pixel row. The row selection unit 12appropriately outputs a transfer signal TRG, a reset signal RST, and aselection signal SEL to the plurality of pixel control lines.

The photodiode 21, an anode electrode of which is connected to a lowpotential side power supply (for example, ground), photoelectricallyconverts received light into a photocharge (herein, photoelectron) of acharge amount corresponding to an amount of the light and accumulatesthe photocharge. A cathode electrode of the photodiode 21 iselectrically connected to a gate of the amplification transistor 24 viathe transfer transistor 22. Here, a region to which the gate of theamplification transistor 24 is electrically connected is a floatingdiffusion (floating diffusion region/impurity diffusion region) FD. Thefloating diffusion FD is a charge-to-voltage conversion unit thatconverts the charge into a voltage.

The transfer signal TRG, a high level (for example, V_(DD) level) ofwhich is active, is applied from the row selection unit 12 to a gate ofthe transfer transistor 22. The transfer transistor 22 becomesconductive in response to the transfer signal TRG, thereby transferringthe photocharge photoelectrically converted by the photodiode 21 andaccumulated in the photodiode 21 to the floating diffusion FD.

The reset transistor 23 is connected between a node of a high potentialside power supply voltage V_(DD) and the floating diffusion FD. Thereset signal RST, a high level of which is active, is applied from therow selection unit 12 to a gate of the reset transistor 23. The resettransistor 23 becomes conductive in response to the reset signal RST,and resets the floating diffusion FD by discharging the charge of thefloating diffusion FD to the node of the voltage V_(DD).

The gate and a drain of the amplification transistor 24 are connected tothe floating diffusion FD and the node of the high potential side powersupply voltage V_(DD), respectively. The amplification transistor 24serves as an input unit of a source follower that reads a signalobtained by photoelectric conversion by the photodiode 21. That is, asource of the amplification transistor 24 is connected to the signalline 32 via the selection transistor 25. Then, the amplificationtransistor 24 and the load current source I connected to one end of thesignal line 32 form a source follower that converts the voltage of thefloating diffusion FD into a potential of the signal line 32.

A drain and a source of the selection transistor 25 are connected to thesource of the amplification transistor 24 and the signal line 32,respectively. The selection signal SEL, a high level of which is active,is applied from the row selection unit 12 to a gate of the selectiontransistor 25. When the selection transistor 25 becomes conductive inresponse to the selection signal SEL, this puts the pixel 20 into aselected state and transmits the signal output from the amplificationtransistor 24 to the signal line 32.

Note that, in the circuit example described above, as a circuitconfiguration of the pixel 20, a 4Tr configuration including thetransfer transistor 22, the reset transistor 23, the amplificationtransistor 24, and the selection transistor 25, that is, the fourtransistors (Tr) is described as an example, but the circuitconfiguration is not limited thereto. For example, a 3Tr configurationin which the selection transistor 25 is omitted and the amplificationtransistor 24 is allowed to have a function of the selection transistor25 is also possible, or the circuit configuration of 5Tr or more inwhich the number of transistors is increased as necessary is alsopossible.

[Semiconductor Chip Structure]

As a semiconductor chip structure of the CMOS image sensor 10 having theconfiguration described above, a flat semiconductor chip structure and astacked semiconductor chip structure may be illustrated. In any CMOSimage sensor 10 having the flat semiconductor chip structure or thestacked semiconductor chip structure, when a substrate surface on a sideon which a wiring layer is arranged of the pixel 20 is set to a frontsurface (front surface), the pixel 20 may have a back-illuminated pixelstructure that captures light applied from a back surface side on theopposite side, or may have a front-illuminated pixel structure thatcaptures light applied from the front surface side. Hereinafter, theflat semiconductor chip structure and the stacked semiconductor chipstructure are described.

(Flat Semiconductor Chip Structure)

FIG. 3 is a plan view schematically illustrating an outline of the flatsemiconductor chip structure of the CMOS image sensor 10. As illustratedin FIG. 3 , the flat semiconductor chip structure is a structure inwhich a circuit portion around the pixel array unit 11 is formed on thesame semiconductor chip (semiconductor substrate) 41 as that of thepixel array unit 11 in which the pixels 20 are arranged in a matrix.Specifically, the row selection unit 12, the constant current sourceunit 13, the column amplifier unit 14, the analog-to-digital conversionunit 15, the horizontal transfer scanning unit 16, the signal processingunit 17, the timing control unit 18 and the like are formed on the samesemiconductor chip 41 as that of the pixel array unit 11.

(Stacked Semiconductor Chip Structure)

FIG. 4 is an exploded perspective view schematically illustrating anoutline of the stacked chip structure of the CMOS image sensor 10. Asillustrated in FIG. 4 , the stacked semiconductor chip structure is astructure in which at least two semiconductor chips (semiconductorsubstrates) of a first-layer semiconductor chip 42 and a second-layersemiconductor chip 43 are stacked. In this stacked structure, the pixelarray unit 11 is formed on the first-layer semiconductor chip 42.Furthermore, the circuit portion such as the row selection unit 12, theconstant current source unit 13, the column amplifier unit 14, theanalog-to-digital conversion unit 15, the horizontal transfer scanningunit 16, the signal processing unit 17, and the timing control unit 18is formed on the second-layer semiconductor chip 43. Then, thefirst-layer semiconductor chip 42 and the second-layer semiconductorchip 43 are electrically connected to each other via connections (VIAs)44A and 44B such as Cu—Cu connection.

According to the CMOS image sensor 10 having the stacked structure, thefirst-layer semiconductor chip 42 is only required to have a size (area)enough for forming the pixel array unit 11, so that the size (area) ofthe first-layer semiconductor chip 42 and eventually a size of an entirechip may be reduced. Moreover, since a process suitable for fabricatingthe pixel 20 may be applied to the first-layer semiconductor chip 42 anda process suitable for fabricating the circuit portion may be applied tothe second-layer semiconductor chip 43, there also is an advantage thata process may be optimized when manufacturing the CMOS image sensor 10.In particular, an advanced process may be applied when fabricating thecircuit portion.

Note that, here, the stacked structure of the two-layer structure formedby stacking the first-layer semiconductor chip 42 and the second-layersemiconductor chip 43 is illustrated, but the stacked structure is notlimited to the two-layer structure, and may be a structure of three ormore layers. Then, in a case of the stacked structure of three or morelayers, the circuit portion such as the row selection unit 12, theconstant current source unit 13, the column amplifier unit 14, theanalog-to-digital conversion unit 15, the horizontal transfer scanningunit 16, the signal processing unit 17, and the timing control unit 18may be formed in a dispersed manner on the semiconductor chip of thesecond and subsequent layers.

[Regarding Single-Slope Analog-to-Digital Converter]

In the CMOS image sensor 10 having the configuration described above,for example, a single-slope analog-to-digital converter has beengenerally used as the analog-to-digital converter in theanalog-to-digital conversion unit 15. Here, the single-slopeanalog-to-digital converter is described.

In the single-slope analog-to-digital converter, a signal of an inclinedwaveform (ramp wave) that linearly changes with a certain inclination isused as a reference signal. The single-slope analog-to-digital convertercompares the analog pixel signal read from the pixel 20 with thereference signal of the ramp wave, amplifies and clips a differencetherebetween, thereby modulating the same to a phase signal, and thenperforms sampling to convert the same into a digital signal. Thissingle-slope analog-to-digital converter has the following problems.

Problem 1

An offset occurs due to a delay at the time of modulation to the phasesignal. Therefore, digital correlated double sampling (CDS) for removingfixed pattern noise of the pixel 20 is indispensable, so that additionaltime for two analog-to-digital conversions and auto-zero is required.

Problem 2

When the pixel signal crosses the reference signal of the ramp wave, athrough current or kickback occurs. Furthermore, crossing time dependson a pixel signal level, and causes interference of other pixel columnswith the analog-to-digital converter.

Problem 3

Since the amplification transistor 24 of the pixel 20 is used to holdthe voltage at the time of analog-to-digital conversion, conversion timelimits a reading speed of the pixel signal.

Regarding problem 1, in the single-slope analog-to-digital converter,auto-zero (offset cancellation by input/output short-circuit) of aninput amplifier is performed to prevent the offset. Therefore, a DCoffset may be removed. However, since the reference signal of the rampwave changes temporally, an AC offset due to a delay cannot be removed.The delay may be reduced by widening a band, but output phase noiseincreases.

Problem 2 is known as a mechanism of an interference phenomenon(streaking) from a bright portion to a dark portion. In the single-slopeanalog-to-digital converter, when a plurality of pixel columns has thesame brightness, switching occurs all at once, so that an influence ofinterference increases.

Problem 3 is a problem caused when sampling of the potential of thesignal line 32 is not performed. In the amplification transistor 24 ofthe pixel 20, relatively large power is consumed to drive the signalline 32 having a large load capacity. Therefore, it is not advisable touse the amplification transistor 24 only to hold the voltage at the timeof the analog-to-digital conversion.

<First Embodiment of Present Disclosure>

In an imaging device (CMOS image sensor as an example) according to afirst embodiment of the present disclosure, a successive approximationregister (SAR) analog-to-digital converter is used as eachanalog-to-digital converter of an analog-to-digital conversion unit 15.The successive approximation register analog-to-digital converter mayoperate at higher speed and with lower power consumption as comparedwith a single-slope analog-to-digital converter having the variousproblems described above. In this embodiment, a column signal processingsystem including the successive approximation register analog-to-digitalconverter may operate at further higher speed and with further lowerpower consumption.

FIG. 5 is a block diagram illustrating an outline of a configuration ofthe CMOS image sensor, which is an example of the imaging deviceaccording to the first embodiment of the present disclosure.

In a CMOS image sensor 10 according to this embodiment, a columnamplifier unit 14 performs processing (CDS processing) of obtaining adifference between a signal component (so-called D-phase voltage) and areset component (so-called P-phase voltage) as a luminance componentinput from each pixel 20 of a pixel array unit 11 via a signal line 32using a reference voltage that defines an auto-zero voltage, and outputsthe difference as a pixel signal. A capacitance unit 19 is providedsubsequent to the column amplifier unit 14.

The capacitance unit 19 differentiates a single-phase signal output fromthe column amplifier unit 14 using the reference voltage that defines azero voltage of an output of the column amplifier unit 14. Then, thecapacitance unit 19 holds the pixel signal input from the columnamplifier unit 14 by, for example, sampling by a switched capacitor. Asuccessive approximation register analog-to-digital conversion unit 15Ais provided subsequent to the capacitance unit 19. The successiveapproximation register analog-to-digital conversion unit 15A includes aplurality of successive approximation register (SAR) analog-to-digitalconverters capable of operating at higher speed and with lower powerconsumption as compared with the single-slope analog-to-digitalconverter, and converts an analog pixel signal input from thecapacitance unit 19 into a digital pixel signal.

According to the CMOS image sensor 10 according to this embodiment, eachsuccessive approximation register analog-to-digital converter of thesuccessive approximation register analog-to-digital conversion unit 15Aperforms a binary search, so that this is more efficient in principlethan the single slope analog-to-digital converter that performs sweep asseen alone. Furthermore, the number of times of analog-to-digitalconversions may be halved by performing the CDS processingconventionally performed by the two analog-to-digital conversions in theanalog-to-digital converter by the column amplifier unit 14 of an analogcircuit system. Moreover, by introducing the sampling by the switchedcapacitor, a potential VSL of the signal line does not need to stand byfor the analog-to-digital conversion, and the sampling is alwaysperformed all at once regardless of the potential VSL of the signal line32, so that an influence of interference due to the switching is alsosmall.

Furthermore, by differentiating the single-phase signal output from thecolumn amplifier unit 14 in the capacitance unit 19, the circuitconfiguration of the capacitance unit 19 and after the same may be madea configuration of a differential circuit. Therefore, in the CMOS imagesensor 10 according to this embodiment, the column signal processingsystem excellent in circuit symmetry may be constructed.

Hereinafter, a specific example of the column signal processing systemin the CMOS image sensor 10 according to the first embodiment,specifically, the column signal processing system including the columnamplifier unit 14, the capacitance unit 19, and the analog-to-digitalconversion unit 15 is described.

First Embodiment

A first embodiment is an example in which a circuit configuration of acapacitance unit and after the same is made a configuration of adifferential circuit. FIG. 6 is a circuit diagram illustrating anoutline of a configuration of a column signal processing systemaccording to the first embodiment. A column amplifier unit 14 includescolumn amplifiers 140 as many as the number of pixel columns provided bythe same number as that of the pixel columns, and a capacitance unit 19includes capacitance multiplexers 190 as many as the number of pixelcolumns. Note that, a plurality of capacitance units 19 and a pluralityof column amplifiers 140 are arranged for one analog-to-digitalconverter to operate as a multiplexer.

(Configuration Example of Column Amplifier)

The column amplifier 140 includes an amplifier 141, a first switch 142,a second switch 143, a third switch 144, a first capacitance element145, and a second capacitance element 146. The first capacitance element145 (hereinafter, simply referred to as the “capacitance element 145”)has a capacitance value CF, and the second capacitance element 146(hereinafter, simply referred to as the “capacitance element 146”) has acapacitance value C_(S).

The amplifier 141 uses a potential VSL (VSL₀ to VSL₇) of a signal line32 as an input of a non-inverting (+) input terminal. The first switch142 (hereinafter, simply referred to as the “switch 142”), one end andthe other end of which are connected to an output terminal of theamplifier 141 and an inverting (−) input terminal of the amplifier 141,respectively, performs an on (close)/off (open) operation according to apolarity (high level/low level) of a switch control signal S_(P).

One end of the second switch 143 (hereinafter, simply referred to as the“switch 143”) is connected to the output terminal of the amplifier 141.One end of the capacitance element 145 is connected to the other end ofthe switch 143, and the other end of the capacitance element 145 isconnected to the other end of the switch 142 and the inverting inputterminal of the amplifier 141. The capacitance element 146 is connectedbetween the other end of the capacitance element 145 and the outputterminal of the amplifier 141, and a node of a reference potential (forexample, ground). The switch 143 performs an on/off operation accordingto a polarity of a switch control signal S_(D).

That is, the switch 143, the capacitance element 145, and thecapacitance element 146 are connected in series in this order betweenthe output terminal of the amplifier 141 and the node of the referencepotential (for example, ground). Furthermore, a common connection nodeN₁ of the capacitance element 145 and the capacitance element 146 iselectrically connected to the other end of the switch 142.

The third switch 144 (hereinafter, simply referred to as the “switch144”), one end of which is connected to a common connection node N2 ofthe switch 143 and the capacitance element 145, performs an on/offoperation according to a polarity of a switch control signal S_(VR). Areference voltage VR that defines a zero voltage of an output of thecolumn amplifier 140 is applied to the other end of the switch 144. Thatis, the switch 144 selectively applies the reference voltage VR to thecommon connection node N2 of the switch 143 and the capacitance element145.

(Configuration Example of Capacitance Multiplexer)

The capacitance multiplexer 190 forming the capacitance unit 19 has aconfiguration of a differential circuit. A positive side of thedifferential circuit includes a switch 191__(P), a capacitance element195__(P), a switch 193__(P), and a switch 194__(P). A negative side ofthe differential circuit includes a switch 191__(M), a capacitanceelement 195__(M), a switch 193__(M), and a switch 194__(M).

The switch 191__(P) on the positive side performs an on (close)/off(open) operation according to a polarity (high level/low level) of aswitch control signal S/N, and samples an output voltage CA_(out) of thecolumn amplifier 140 applied to one end when turned on. The switch191__(M) on the negative side performs an on/off operation according tothe polarity of the switch control signal S/N, and samples the referencevoltage VR applied to one end when turned on.

Here, the reference voltage VR sampled by the switch 191__(M) on thenegative side is used as a voltage on the negative side of thedifferential circuit. In this manner, in the capacitance multiplexer190, the single-phase signal input from the column amplifier 140 may bedifferentiated by using the reference voltage VR sampled by the switch191__(M) on the negative side as a reference. As a result, the circuitconfiguration of the capacitance unit 19 and after the same may be madethe configuration of the differential circuit.

On the positive side of the differential circuit, one end of thecapacitance element 195__(P) is connected to the other end of the switch191__(P), and one ends of the switch 193__(P) and the switch 194__(P)are connected to the other end of the capacitance element 195__(P). Thecapacitance element 195__(P) is charged with the output voltage CA_(out)of the column amplifier 140 sampled by the switch 191__(P). An outputcommon mode reference voltage V_(CM) of a preamplifier 151 in asuccessive approximation register analog-to-digital converter 150 to bedescribed later is applied to the other end of the switch 193__(P). Theother end of the switch 194__(P) serves as an output end on the positiveside of the capacitance multiplexer 190.

On the negative side of the differential circuit, one end of thecapacitance element 195__(M) is connected to the other end of the switch191__(M), and one ends of the switch 193__(M) and the switch 194__(M)are connected to the other end of the capacitance element 195__(M). Thecapacitance element 195__(M) is charged with the reference voltage VRsampled by the switch 191__(M). The output common mode reference voltageV_(CM) is applied to the other end of the switch 193__(M). The other endof the switch 194__(M) serves as an output end on the negative side ofthe capacitance multiplexer 190.

An inter-differential short-circuit switch (fourth switch) 192 isconnected between one ends of the capacitance element 195__(P) on thepositive side and the capacitance element 195__(M) on the negative side.The inter-differential short-circuit switch 192 performs an on/offoperation according to a polarity of a switch control signal S_(VMI).Specifically, when transferring the output voltage CA_(out) of thecolumn amplifier 140 held by the capacitance element 195__(P) and thereference voltage VR held by the capacitance element 195__(M) to thesubsequent successive approximation register analog-to-digital converter150 via the switch 194__(P) and the switch 194__(M), theinter-differential short-circuit switch 192 is turned on toshort-circuit one end (input end) of the capacitance element 195__(P)and one end (input end) of the capacitance element 195__(M).

In this manner, by short-circuiting the input ends (differentials) ofthe capacitance element 195__(P) and the capacitance element 195__(M) bythe inter-differential short-circuit switch 192, it is possible toprevent an influence of a voltage (in-phase component) on the columnamplifier 140 side from reaching the circuit after the capacitanceelement 195__(P) and the capacitance element 195__(M). Incidentally, arelatively high voltage is used on the column amplifier 140 side. Incontrast, the successive approximation register analog-to-digitalconverter 150 subsequent to the capacitance multiplexer 190 is requiredto operate at a low voltage and at a high speed. Therefore, in order tosecure high-speed operation at a low voltage required for the successiveapproximation register analog-to-digital converter 150, it is importantto prevent an influence of a relatively high voltage on the columnamplifier 140 side from reaching the circuit after the capacitanceelement 195__(P) and the capacitance element 195__(M) by an action ofthe inter-differential short-circuit switch 192.

In the column signal processing system illustrated in FIG. 6 , by theaction of the inter-differential short-circuit switch 192, each switchof a circuit portion X including the column amplifier 140 and thecapacitance multiplexer 190 may be formed using a thick-filmhigh-voltage transistor having a relatively thick film, and each switchof the capacitance multiplexer 190 may be formed using a thin-filmlow-voltage transistor having a relatively thin film. However, since theinfluence of the relatively high voltage on the column amplifier 140side does not reach the circuit after the capacitance element 195__(P)and the capacitance element 195__(M) due to the action of theinter-differential short-circuit switch 192, in principle, each switchafter the capacitance element 195__(P) and the capacitance element195__(M) of the capacitance multiplexer 190 may also be formed using athin-film low-voltage transistor having a relatively thin film.

Furthermore, by shifting the voltage (in-phase component) on the columnamplifier 140 side to a low voltage by the action of theinter-differential short-circuit switch 192, a comparator of a lowbreakdown voltage may be used in the successive approximation registeranalog-to-digital converter 150. Moreover, since a differentialcapacitance (capacitance array unit C_(DAC)) is separated from thecolumn amplifier 140 and other reference voltages at the time ofanalog-to-digital conversion, a high-speed operation of theanalog-to-digital conversion becomes possible.

(Configuration Example of Successive Approximation RegisterAnalog-to-Digital Converter)

The successive approximation register analog-to-digital converter 150includes the preamplifier 151, a comparator 152, a SAR logic unit 153, adigital-to-analog converter (DAC) 154, and the capacitance array unitC_(DAC).

The preamplifier 151 includes an amplifier 1511 and switches 1512__(P)and 1512__(M). The amplifier 1511 uses an analog voltage PAIN+ (outputvoltage CA_(out) of the column amplifier 140) supplied from thecapacitance multiplexer 190 as an input of an inverting (−) inputterminal, and uses an analog voltage PAIN-(reference voltage VR) as aninput of a non-inverting (+) input terminal.

The switches 1512__(P) and 1512__(M) are switches of auto-zero (offsetcancellation by input/output short-circuit), and perform an on/offoperation according to a polarity of a switch control signal S_(AZ). Theswitch 1512__(P) is connected between the inverting input terminal andan output terminal of the preamplifier 151. The switch 1512__(M) isconnected between the non-inverting input terminal and the outputterminal of the preamplifier 151.

The comparator 152 compares magnitude of the analog voltage supplied viathe preamplifier 151 with magnitude of a comparison reference voltage insynchronization with a comparator clock CKI, and supplies a comparisonresult to the SAR logic unit 153.

The SAR logic unit 153 includes, for example, an N-bit successiveapproximation register, stores the comparison result of the comparator152 for each bit in synchronization with a clock CK, and outputs thesame as an N-bit digital value D_(OUT) after the analog-to-digitalconversion.

The digital-to-analog converter 154 and the capacitance array unit 155form an N-bit capacitance digital-to-analog converter. Then, in thecapacitance digital-to-analog converter, the N-bit digital value D_(OUT)output from the SAR logic unit 153 is converted into an analog voltageand is applied to the inverting (−) input terminal of the amplifier 1511as an input thereof.

(Circuit Operation of Column Signal Processing System)

Subsequently, a circuit operation of the column signal processing systemaccording to the first embodiment including the column amplifier 140,the capacitance multiplexer 190, and the successive approximationregister analog-to-digital converter 150 having the configurationdescribed above is described with reference to a timing chart in FIG. 7.

The timing chart in FIG. 7 illustrates a timing relationship among theswitch control signals S_(P) and S_(VR), the switch control signalsS_(D), S_(IN), and S_(VMA), and the switch control signals S_(VMI) andS_(SUM). The timing chart in FIG. 7 further illustrates waveformdiagrams of the potential VSL of the signal line 32, the referencevoltage VR, and the output voltage CA_(out) of the column amplifier 140.

In a period T₁, the switch control signal S_(P) and the switch controlsignal S_(VR) are put into a high level in a state in which thepotential VSL of the signal line 32 is a reset component (P-phasevoltage), so that the switch 142 and the switch 144 are turned on(closed). Therefore, the capacitance element 145 and the capacitanceelement 146 are charged with the reset component (P-phase voltage). Atthat time, the voltage of the common connection node N2 of the switch143 and the capacitance element 145 is the same voltage as the referencevoltage VR. The reset component (P-phase voltage) greatly variesdepending on the pixel 20 (with low accuracy), but since the referencevoltage VR is generated on the column amplifier 140 side, variation issmall (with high accuracy).

Next, in a period T2, the switch control signal S_(P) and the switchcontrol signal S_(VR) are put into a low level, so that the switch 142and the switch 144 are turned off (opened), and simultaneously, theswitch control signal S_(D) is put into a high level, so that the switch143 is turned on (closed). At that time, a non-inverting amplifiercircuit is formed using the capacitance element 145, the capacitanceelement 146, and the amplifier 141, and an output voltage V_(out) of thecolumn amplifier 140 is substantially the same voltage as the referencevoltage VR.

When the potential VSL of the signal line 32 drops to a signal component(D-phase voltage), which is a luminance component, feedback is appliedso that the voltage of the common connection node N₁ of the capacitanceelement 145 and the capacitance element 146 becomes the same voltage asthe signal component (D-phase voltage).

By this series of operations, the CDS processing of obtaining adifference between the reset component (P-phase voltage) and the signalcomponent (D-phase voltage) is performed, and the output voltage V_(out)of the column amplifier 140 drops by a voltage obtained by amplifyingthe potential VSL of the signal line 32 by (C_(F)+C_(S))/C_(F). Sincethe variation in the reference voltage VR is small, a gain of the columnamplifier 140 may be increased.

In the period T₂, the switch control signal S_(IN) and the switchcontrol signal S_(VMA) are put into a high level simultaneously with theswitch control signal S_(D). Therefore, the switches 191__(P) and191__(M) are turned on, the output voltage V_(out) of the columnamplifier 140 and the reference voltage VR are sampled as a differentialvoltage, and the capacitance elements 195__(P) and 195__(M) are chargedwith the same.

At the same time, the switches 193__(P) and 193__(M) are turned on toapply the output common mode reference voltage V_(C)N to an output side(the successive approximation register analog-to-digital converter 150side) of the capacitance elements 195__(P) and 195__(M). The outputcommon mode reference voltage V_(CM) is set to the same voltage as anin-phase voltage of the preamplifier 151 in the successive approximationregister analog-to-digital converter 150.

Thereafter, in a period T3, the switch control signal S_(VMI) and theswitch control signal S_(SUM) are put into a high level, so that theswitch 192 and the switches 194__(P) and 194__(M) are turned on, and thedifferential voltage with which the capacitance elements 195__(P) and195__(M) are charged is transferred to the successive approximationregister analog-to-digital converter 150.

When the switch 192 is turned on, an input side of the capacitanceelements 195__(P) and 195__(M) is subjected to differentialshort-circuit, but put into an open state in terms of the in-phasecomponent. Therefore, the in-phase component of the input is nottransmitted to the successive approximation register analog-to-digitalconverter 150. Therefore, the preamplifier 151 in the successiveapproximation register analog-to-digital converter 150 may be formedusing a high-speed thin-film low-voltage transistor.

When the differential voltage with which the capacitance elements195__(P) and 195__(M) are charged is transmitted to the successiveapproximation register analog-to-digital converter 150, the comparatorclock CKI is input to the comparator 152 to start the comparison. Thecomparison result of the comparator 152 is fed back to thedigital-to-analog converter 154 via the SAR logic unit 153, and issubjected to a binary search so that the input of the preamplifier 151becomes 0 V. Finally, almost all the charges accumulated in thecapacitance elements 195__(P) and 195__(M) of the capacitancemultiplexer 190 are transferred to the capacitance array unit C_(DAC),and the input of the digital-to-analog converter 154 at that time isobtained as an output code.

Example 2

Example 2 is an implementation example of a column signal processingsystem, and an example in which a capacitance unit 19 (capacitancemultiplexer 190) and after the same form a configuration of adifferential circuit. FIG. 8 is a circuit diagram illustrating anoutline of a configuration of the column signal processing systemaccording to Example 2.

In the column signal processing system according to Example 2, anexample of a configuration of processing potentials VSL₀ to VSL₇ of aplurality of signal lines 32, for example, eight signal lines 32,respectively, by multiplying via eight column amplifiers 140 arranged inparallel corresponding to the eight signal lines 32 and four capacitancemultiplexers 190 arranged in parallel for one successive approximationregister analog-to-digital converter 150 of a successive approximationregister analog-to-digital conversion unit 15A is described.

Furthermore, in the column signal processing system according to Example2, the potentials VSL₀ to VSL₇ of the eight signal lines 32,respectively, are handled by being divided into the potentials VSL₀ toVSL₃ of the four signal lines 32 in a first half and the potentials VSL₄to VSL₇ of the four signal lines 32 in a second half.

FIG. 8 illustrates a reference voltage generation unit 160 thatgenerates a reference voltage used in the column amplifier 140, thecapacitance multiplexer 190, and the successive approximation registeranalog-to-digital converter 150. The reference voltage generation unit160 includes a first amplifier unit 161, a second amplifier unit 162,and a third amplifier unit 163. The column amplifier 140 outputs asignal in a D phase. Therefore, sampling by the three capacitanceelements (195__(A), 195__(B), and 195__(C)) is performed only in the Dphase. In contrast, comparison by a comparator 152 is continuouslyperformed in both a P phase and the D phase. The potentials VSL₀ to VSL₃of the signal lines 32 are subjected to analog-to-digital conversion inthe immediately subsequent P phase, and the potentials VSL₄ to VSL₇ ofthe signal lines 32 are subjected to analog-to-digital conversion in thesecond D phase. In the second D phase, since the capacitance element195B is used for the analog-to-digital conversion, an output of thecolumn amplifier 140 at that time is sampled by available capacitanceelement 195__(C) and capacitance element 195__(A). At that time, thepotentials VSL₄ to VSL₇ of the signal lines 32 different from theprevious one us sampled by the capacitance element 195__(A). Byrepeating this operation, the same capacitance element is not used forthe potential VSL of a specific signal line 32.

The first amplifier unit 161 generates the reference voltage VR thatdefines a zero voltage of the output of the column amplifier 140. Thereference voltage VR is supplied to the column amplifier 140 via avoltage line L₁. The second amplifier unit 162 supplies an output commonmode reference voltage V_(CM) of a preamplifier 151 to the capacitancemultiplexer 190 via a voltage line L₂. The output common mode referencevoltage V_(CM) is also supplied to the successive approximation registeranalog-to-digital converter 150 via a voltage line L₃. The thirdamplifier unit 163 generates a high voltage VH, a medium voltage VM, anda low voltage VL to be used by a capacitance array unit (C_(DAC)) 155.The high voltage VH, the medium voltage VM, and the low voltage VL aresupplied to the capacitance array unit (C_(DAC)) 155 via voltage linesL₄, L₅, and L₆.

In the P phase, the capacitance element 145 of the column amplifier 140is charged, and in the D phase, the charge with which the capacitanceelement 145 is charged is used as a signal input on a negative side ofthe capacitance multiplexer (CMUX) 190. The capacitance multiplexer 190is configured by differential. Switches 192__(A), 192__(B), and 192__(C)on the input side short-circuit the differentials at the time ofcomparison of the comparator 152, and are not connected to a commonnode. In this manner, an input side of the capacitance multiplexer 190is completely separated at the time of comparison of the comparator 152,so that settling of the capacitance array unit (C_(DAC)) 155 in thesuccessive approximation register analog-to-digital converter 150 may beaccelerated.

Switches 193__(AP) and 193__(AM), switches 193__(BP) and 193__(BM), andswitches 193__(CP) and 193__(CM) on an output side of the capacitancemultiplexer 190 are connected to the voltage line L₂ that transmits theoutput common mode reference voltage V_(CM), and are turned on at thetime of sampling. The output common mode reference voltage V_(CM) is thesame voltage as an input operation potential of the preamplifier 151.

The high voltage VH, the medium voltage VM, and the low voltage VLgenerated by the third amplifier unit 163 are the reference voltages ofthe capacitance array unit (C_(DAC)) 155. Since the capacitance arrayunit (C_(DAC)) 155 operates at a high speed when the comparator 152compares, the high voltage VH and the low voltage VL are required to beable to respond at a high speed and to have a low impedance.

(Power Supply Voltage and Used Transistor)

Here, for a specification of a power supply voltage, for example, 2.8 V(V_(DD)_H) and 0.8 V (V_(DD)_L) are assumed. Among them, 2.8 V is thesame as the voltage used in a pixel 20, and is used for a circuit of ahigh breakdown voltage transistor. Furthermore, 0.8 V is assumed to be avoltage used in a logic circuit. Since the potential VSL of the signalline 32 is 2 V or larger at maximum, this cannot be handled by a lowbreakdown voltage transistor. Therefore, the column amplifier 140 needsto include a high breakdown voltage transistor. Since the successiveapproximation register analog-to-digital converter 150 requires ahigh-speed comparison operation, this desirably includes a low breakdownvoltage transistor. However, it is necessary to pay attention to a largeleakage current of the low breakdown voltage transistor.

In the preamplifier 151 of the successive approximation registeranalog-to-digital converter 150, since channel leakage of a switch 1512of auto-zero (offset cancellation due to input/output short-circuit)affects linearity, it is necessary to take a measure such as increasinga channel length L. Since gate leakage of the input differential pair ofthe comparator 152 might also affect a characteristic, it is sometimesnecessary to suppress the leakage using the high breakdown voltagetransistor.

Furthermore, when a plurality of power supplies is involved betweenloops of the successive approximation register analog-to-digitalconverter 150, an operation margin for absorbing variations betweendifferent power supplies is required, so that it is important to formusing a single power supply. The high voltage VH and the low voltage VLare set to 0.8 V (V_(DD)_L) and the same voltage as ground,respectively, in order to sufficiently apply a gate voltage to theswitches forming the capacitance array unit (C_(DAC)) 155. Since theoutput of the column amplifier 140 has a high voltage, all the switchesforming the capacitance multiplexer 190 are formed using high breakdownvoltage transistors.

(Regarding Level Diagram)

FIG. 9 illustrates a level diagram. A voltage range of the potential VSLof the signal line 32 varies depending on a sensor specification, buthere, it is assumed that the voltage drops according to brightness with2 V as a reference and drops by 450 mV at the maximum. The potential VSLof the signal line 32 is amplified by the column amplifier 140; as again is higher, noise of the subsequent successive approximationregister analog-to-digital converter 150 is suppressed, and noise of thecolumn amplifier 140 itself is also reduced, so that it is desirable totake as large gain as possible. However, since the power supply voltageis 2.8 V, it is necessary to suppress the output of the column amplifier140 within a range obtained by adding an operation range of the circuitand a margin to this.

Here, the gain is set to four times, and the range is 1.8 V with respectto 2.8 V. An input of the successive approximation registeranalog-to-digital converter 150 is a differential voltage, and anegative-side input is fixed to the reference voltage. When the pixel 20has brightness of zero, the differential of 0 V is the input of thesuccessive approximation register analog-to-digital converter 150, and anegative differential voltage is applied as the pixel becomes brighter(that is, the potential VSL of the signal line 32 decreases). Arelationship with an output code of the successive approximationregister analog-to-digital converter 150 is such that the differentialof 1.8 V corresponds to ¾ full scale, and ⅞ full scale is output when 0V is input.

For a small input signal, input conversion noise may be reduced byincreasing the gain. As illustrated in FIG. 9 , when the gain is set toeight times (×8), the input range is halved. Moreover, the gain may beincreased; however, a contribution of the column amplifier 140 isdominant in the input conversion noise, so that an advantage of settingthe gain larger than eight times is small.

(Regarding Timing)

All dynamic signals that drive the column signal processing system needto be implemented as differential signals. In a case where the columnamplifier 140 side is a switch, a dummy for canceling injection using adifferential signal is prepared. If this is not observed, a return ofthe control signal passes through a common power supply and the like,which might cause unexpected interference. Furthermore, regarding a gatesignal of the switch (switch control signal), it is necessary to preventthe switches of different phases from being turned on at the same time(non-overlap).

Moreover, a switch control signal S_(D) of a switch 143 of the columnamplifier 140, a switch control signal S_(IN0X) of a switch 191__(0x)(X=A, B, C) of the capacitance multiplexer 190, a switch control signalS_(IN1X) of a switch 191__(1X), and a switch control signal S_(VMIX) ofa switch 1931__(X) are desirably delayed from other switch controlsignals while maintaining non-overlap.

Hereinafter, a specific configuration example of the column amplifier140 and the successive approximation register analog-to-digitalconverter 150 is described.

(Configuration Example of Column Amplifier)

Here, as an example of a specific configuration of the column amplifier140, a current reuse column amplifier (CRCA) is illustrated. Since thecurrent reuse column amplifier performs voltage amplification using abias current of the signal line 32, a non-inverting column amplifier oflow power consumption may be implemented. A circuit diagram of anexample of a configuration of the current reuse column amplifier isillustrated in FIG. 10 .

A current reuse column amplifier 1400 includes a current amplificationtransistor 1401, current source transistors 1402 and 1403, cascodetransistors 1404 and 1405, switches 1406, 1407, and 1408, a referenceside capacitance element 1409, and a feedback capacitance element 1410.

Here, a P-channel MOS field effect transistor is used, for example, asthe current amplification transistor 1401, the current source transistor1403, and the cascode transistor 1404. Furthermore, an N-channel MOSfield effect transistor is used, for example, as the current sourcetransistor 1402 and the cascode transistor 1405.

The current amplification transistor 1401 and the current sourcetransistor 1402 are connected in series between the signal line 32 and anode of a reference potential (for example, ground) in this order. Thatis, a source electrode of the current amplification transistor 1401 isconnected to the signal line 32. A predetermined bias voltage nbias isapplied to a gate electrode of the current source transistor 1402.Therefore, the current source transistor 1402 applies a constant biascurrent corresponding to a predetermined bias voltage nbias to thesignal line 32.

The current source transistor 1403, the cascode transistor 1404, and thecascode transistor 1405 are connected in series between a node of thepower supply voltage V_(DD) and a drain electrode of the current sourcetransistor 1402 in this order. A predetermined bias voltage pbias isapplied to a gate electrode of the current source transistor 1403, apredetermined bias voltage pcas is applied to a gate electrode of thecascode transistor 1404, and a predetermined bias voltage ncas isapplied to a gate electrode of the cascode transistor 1405.

The switch 1406 is connected between a gate electrode of the currentamplification transistor 1401 and a drain electrode of the cascodetransistor 1404 (drain electrode of the cascode transistor 1405), andperforms an on (closed)/off (open) operation according to a polarity ofa switch control signal S_(P).

The reference side capacitance element 1409 is connected between thegate electrode of the current amplification transistor 1401 and the nodeof the reference potential (for example, ground). One end of thefeedback capacitance element 1410 is connected to the gate electrode ofthe current amplification transistor 1401.

A switch 1047 is connected between the other end of the feedbackcapacitance element 1410 and the drain electrode of the cascodetransistor 1404 (the drain electrode of the cascode transistor 1405),and performs an on/off operation according to a polarity of a switchcontrol signal S_(D).

A switch 1408, one end of which is connected to a common connection nodeN₁₁ of the feedback capacitance element 1410 and the switch 1047,performs an on/off operation according to a polarity of a switch controlsignal S_(VR). The reference voltage VR is applied to the other end ofthe switch 1408. Therefore, the switch 1408 selectively applies thereference voltage VR to the common connection node N₁₁ under the controlof the switch control signal S_(VR).

With the configuration described above, the current reuse columnamplifier 1400 in which the source electrode of the currentamplification transistor 1401 serves as a (+) input end, the gateelectrode serves as a (−) input end, and a common connection node N₁₂between the cascode transistor 1404 and the cascode transistor 1405serves as an output end is configured. Since the current amplificationtransistor 1401 uses the bias current of the signal line 32, it ispossible to efficiently perform voltage amplification.

In the current reuse column amplifier 1400 having the configurationdescribed above, in a correspondence relationship with the columnamplifier 140 illustrated in FIG. 6 , the switch 1406 corresponds to theswitch 142 in FIG. 6 , the switch 1407 corresponds to the switch 143 inFIG. 6 , and the switch 1408 corresponds to the switch 144 in FIG. 6 .Furthermore, the reference side capacitance element 1409 corresponds tothe capacitance element 146 having the capacitance value C_(S), and thefeedback capacitance element 1410 corresponds to the capacitance element145 having the capacitance value C_(F).

(Configuration Example of Successive Approximation RegisterAnalog-to-Digital Converter)

The successive approximation register analog-to-digital converter 150 isexcellent in power efficiency. A detailed circuit diagram of thesuccessive approximation register analog-to-digital converter 150 isillustrated in FIG. 11 .

The circuit of the successive approximation register analog-to-digitalconverter 150 is configured by complete differential. In a generalsuccessive approximation register analog-to-digital converter, an inputcapacitance for sampling an input voltage and a DAC capacitance(C_(DAC)) are often integrated, but here, they are separated formultiplexing.

FIG. 11 also illustrates an input capacitance unit (hereinafter, forconvenience, referred to as a “capacitance multiplexer 190”) that alsoserves as the capacitance multiplexer 190. Here, for the sake ofsimplicity, only one of a plurality of input capacitance units (190) isillustrated.

In the capacitance multiplexer 190, at the time of sampling, theswitches 191__(P) and 191__(M) and the switches 193__(P) and 193__(M)are turned on (closed) to charge the capacitance elements 195__(P) and195__(M) with charges. At the time of analog-to-digital conversion, theswitch 192 and the switches 194__(P) and 194__(M) are turned on(closed), so that the capacitance multiplexer 190 is connected to thesuccessive approximation register analog-to-digital converter 150.

The switch 192 is not connected to a specific reference potential, andonly short-circuits differentials. This is to prevent fluctuation of anin-phase potential on the preamplifier 151 side due to an input in-phasepotential. When an output in-phase potential of the preamplifier 151 andthe output common mode reference voltage V_(CM) are made the same, theinput in-phase potential of the preamplifier 151 is always the same asthe output common mode reference voltage V_(CM).

Since the output of the column amplifier 140 is single-ended, the inputin-phase potential fluctuates depending on the signal, but the inputin-phase potential of the preamplifier 151 does not change, so thatlinearity is improved. The input side is the output (2.4 V to 0.6 V) ofthe column amplifier 140 and the reference voltage VR (2.4 V), but sincethe output common mode reference voltage V_(CM) is fixed at about 0.5 V,the preamplifier 151 of a low voltage (V_(DD)_L) may be used.

Although the input voltage is as high as 1.8 V, this is connected inseries with the DAC capacitance (C_(DAC)) at the time of chargetransfer, so that the input voltage of the preamplifier 151 issufficiently attenuated. In this manner, by managing thein-phase/differential voltage, those other than the capacitancemultiplexer 190 may be formed using a thin-film low-voltage transistorhaving a relatively thin film. Incidentally, all the switches of thecapacitance multiplexer 190 are formed using thick-film high-voltagetransistors having a relatively thick film.

All the switches of the preamplifier 151, the comparator 152, the SARlogic unit 153, and the DAC capacitance (C_(DAC)) in a comparison loopof the successive approximation register analog-to-digital converter 150use the transistors of the same power supply voltage and the same filmthickness, so that a high-speed operation becomes possible.

Furthermore, it is also important that, at the time of the operation ofthe SAR logic unit 153, this is completely separated from the columnamplifier 140 and reference nodes other than the high voltage VH/lowvoltage VL. Since these nodes are not of so fast and low impedance, itis necessary not to affect the settling of the DAC capacitance(C_(DAC)).

As illustrated in FIG. 11 , the capacitance array of the DAC capacitance(C_(DAC)) includes 14 capacitances grouped into six, four, and four. Thefirst six-bit group is set as MSB, the middle four-bit group is set asLSB1, and the last four-bit group is set as LSB0. Each group isseparated by a bridge capacitance element, and a weight per capacitanceelement changes. When the weight of MSB is set to 1, that of LSB1 is ⅛and that of LSB0 is 1/32.

The weights of the most significant bit in LSB1 and the leastsignificant bit in MSB have the same value to have redundancy. LSB0similarly overlaps the most significant bit. Since the redundancy is oftwo bits in total, bit accuracy of the successive approximation registeranalog-to-digital converter 150 is finally of 12 bits. The redundancy isfor compensating for insufficient settling of higher-order bits and forcorrecting nonlinearity due to variation in bridge capacitance elements.

In order to widen a range of redundancy, redundant bits should beinserted in a high-order as possible, but there is a trade-off ofincreasing the number of capacitance elements, and noise increases.Furthermore, in order to correct variation in bridge capacitanceelements, the redundant bits need to be inserted into each group.

A capacitance value CB of the bridge capacitance element may beexpressed by the following equation, where a ratio of weight to alower-order group is set to α (<1), and the total capacitance value ofthe lower-order group (including further lower-order substantialcapacitance value) is set to C_(TL).

C _(B) =C _(TL)/{(1/α)−1}

Determining the weight of the entire lower-order bits, when a ratio ofthe bridge capacitance element to a unit capacitance element isdeviated, this causes nonlinearity. Therefore, it is necessary toimplement so as not to deviate as much as possible, but it is difficultto make the ratio of the bridge capacitance element to the unitcapacitance element the same because this is not integral multiple andthere is no continuity in layout. Therefore, it is considered necessaryto perform digital correction to multiply a non-integer correctioncoefficient for each group.

<Second Embodiment of Present Disclosure>

The two capacitance elements 195__(P) and 195__(M) in the capacitanceunit 190 in FIG. 6 hold different charges, and when a subsequent side ofthe column amplifier 140 is seen from the signal line VSL, thecapacitance elements 195__(P) and 195__(M) act as loads obtained bymultiplying by the gain of the column amplifier 140, and settling timeof VSL becomes long. Therefore, a capacitance unit 190 according to asecond embodiment to be described below is subjected to a measure forshortening settling time.

FIG. 12 is a circuit diagram illustrating an internal configuration ofthe capacitance unit 19 according to the second embodiment. Although acolumn amplifier 140 connected to a preceding side of the capacitanceunit 19 and a successive approximation register analog-to-digitalconverter 150 connected to a subsequent side of the capacitance unit 19are not illustrated in FIG. 12 , the column amplifier 140 and thesuccessive approximation register analog-to-digital converter 150similar to those in FIG. 6 may be connected to the capacitance unit 19in FIG. 12 .

The capacitance unit 19 in FIG. 12 includes a first node n1, a secondnode n2, a positive-side capacitance element 195__(P), a negative-sidecapacitance element 195__(M), a fourth switch 192, a fifth switch 196, asixth switch 194__(P), a seventh switch 194__(M), a switch 191__(P), anda switch 191__(M).

A pixel signal from the column amplifier 140 is supplied to the firstnode n1. A reference voltage VR is supplied to the second node n2. Morespecifically, the pixel signal input from the column amplifier 140 issupplied to the first node n1 via the switch 191__(P). Furthermore, thereference voltage VR is supplied to the second node n2 via the switch191__(M).

The positive-side capacitance element 195__(P) and the negative-sidecapacitance element 195__(M) are connected in series between the firstnode n1 and the second node n2. In this manner, by connecting thepositive-side capacitance element 195 p and the negative-sidecapacitance element 195__(M) in series between the first node n1 and thesecond node n2, it is possible to reduce an effective capacitance when asubsequent side of the column amplifier 140 is seen from a signal lineVSL.

The fourth switch 192 selectively short-circuits the first node n1 andthe second node n2. The fourth switch 192 performs an on/off operationaccording to a polarity of a switch control signal SREFH. When thefourth switch 192 is put into a closed state, the first node n1 and thesecond node n2 are short-circuited.

The fifth switch 196 selectively applies a common mode reference voltageVM of the successive approximation register analog-to-digital converter150 to a common connection node n5 of the positive-side capacitanceelement 195__(P) and the negative-side capacitance element 195__(M).When the fifth switch 196 is put into a closed state, the common modereference voltage VM is applied to the common connection node n5.

The sixth switch 194__(P) selectively connects the second node n2 to afirst input end n11 of the successive approximation registeranalog-to-digital converter 150. The seventh switch 194__(M) selectivelyconnects the first node n1 to a second input end n12 of the successiveapproximation register analog-to-digital converter 150.

FIG. 13 is a timing chart of the capacitance unit 19 in FIG. 12 . FIG.13 illustrates timings of switch control signals S_(P) and S_(VR) ofswitches 142 and 144, respectively, and a switch control signal S_(D) ofa switch 143 in the column amplifier 140, a switch control signal SINHof the switches 191__(P) and 191__(M), a switch control signal SVMH ofthe fifth switch 196, the switch control signal SREFH of the fourthswitch 192, a switch control signal SSUMH of the switches 194__(P) and194__(M), and a switch control signal SRAZ of switches 1512__(P) and1512__(M) in the successive approximation register analog-to-digitalconverter 150.

Time t1 to t2 in FIG. 13 is immediately before a period in which thecapacitance unit 19 samples a voltage of the signal line VSL. Time t2 tot3 is the period in which the capacitance unit 19 samples the voltage ofthe signal line VSL. Time t3 to time t4 is immediately before a periodin which the pixel signal held by the capacitance unit 19 is transferredto the successive approximation register analog-to-digital converter150, and is an auto-zero (offset cancellation due to input/outputshort-circuit) period of a preamplifier 151. Time t4 to t5 is a periodin which the pixel signal held by the capacitance unit 19 is transferredto the successive approximation register analog-to-digital converter150. Time t5 to t6 is a period in which the successive approximationregister analog-to-digital converter 150 performs AD conversion. Aseries of processing from time t1 to time t6 is repeated after time t6.

The switches 191__(P) and 191__(M) are put into a closed state in theperiod from time t1 to time t3. Therefore, the pixel signal output fromthe column amplifier 140 and the reference voltage VR are supplied tothe capacitance unit 19 from immediately before the capacitance unit 19samples the voltage of the signal line VSL to the end of a samplingperiod.

The fifth switch 196 is put into a closed state in the period from timet1 to time t2 and the period from time t4 to time t5. Therefore, thecommon mode reference voltage VM is applied to the common connectionnode n5 of the positive-side capacitance element 195__(P) and thenegative-side capacitance element 195__(M) immediately before the periodin which the capacitance unit 19 samples the voltage of the signal lineVSL, and in the period in which the pixel signal held by the capacitanceunit 19 is transferred to the successive approximation registeranalog-to-digital converter 150.

The fourth switch 192 is put into a closed state in the period from timet1 to time t2. Therefore, the first node n1 and the second node n2 aretemporarily short-circuited immediately before the period in which thecapacitance unit 19 samples the voltage of the signal line VSL.

The switches 194__(P) and 194__(M) are put into a closed state in theperiod from time t4 to time t5, and the pixel signal held by thecapacitance unit 19 is transferred to the successive approximationregister analog-to-digital converter 150.

As indicated by a broken line in FIG. 12 , a parasitic capacitance Cp3exists at the common connection node n5. Since the fifth switch 196 isturned on and applies the common mode reference voltage VM to the commonconnection node n5 at times t1 to t2 immediately before the capacitanceunit 19 samples the voltage of the signal line VSL, a potential of thecommon connection node n5 may be determined without an influence of theparasitic capacitance Cp3 of the common connection node n5.

However, as indicated by broken lines in FIG. 12 , parasiticcapacitances Cp1 and Cp2 also exist at the first node n1 and the secondnode n2, respectively. Due to the parasitic capacitances Cp1 and Cp2, acommon voltage of a differential signal transferred to the successiveapproximation register analog-to-digital converter 150 has input signaldependency.

FIG. 14 is a diagram illustrating the input signal dependency of thedifferential signal transferred from the capacitance unit 19 to thesuccessive approximation register analog-to-digital converter 150 inFIG. 12 . In FIG. 14 , a voltage level of the signal line VSL is plottedalong the abscissa, and a voltage level of the differential signal isplotted along the ordinate. FIG. 14 illustrates graphs gp1, gp2, and gp3illustrating the input signal dependency of differential signals compinpand compinn of the nodes n11 and n12, and a common voltage of thedifferential signals, respectively. As illustrated, the larger thevoltage level of the signal line VSL, the larger a fluctuation amount ofthe differential signals compinp and compinn and the common voltagecommon of the differential signal.

In this manner, in the capacitance unit 19 in FIG. 12 , since thepositive-side capacitance element 195__(P) and the negative-sidecapacitance element 195__(M) are connected in series between the firstnode n1 to which the pixel signal from the column amplifier 140 is inputand the second node n2 to which the reference voltage VR is supplied,the effective capacitance when the subsequent side of the columnamplifier 140 is seen from the signal line VSL may be reduced. However,since the parasitic capacitances Cp1 and Cp2 exist at the first node n1and the second node n2, respectively, the common voltage of thedifferential signal transferred from the capacitance unit 19 to thesuccessive approximation register analog-to-digital converter 150 mightfluctuate due to the influence, and a measure therefor is describedbelow.

(First Variation of Capacitance Unit 19)

FIG. 15 is a circuit diagram illustrating an internal configuration of acapacitance unit 19 according to a first variation of FIG. 12 . Thecapacitance unit 19 in FIG. 15 includes a positive-side capacitanceelement 195__(P), a negative-side capacitance element 195__(M), a 4aswitch 192 a, a 4b switch 192 b, a 5a switch 196 a, a 5b switch 196 b, a5c switch 196 c, a sixth switch 194__(P), a seventh switch 194__(M), aswitch 191__(P), and a switch 191__(M). Hereinafter, a difference fromthe capacitance unit 19 in FIG. 12 is mainly described.

The 4a switch 192 a and the 4b switch 192 b are connected in seriesbetween a first node n1 and a second node n2. When the 4a switch 192 aand the 4b switch 192 b are put into a closed state, the first node n1and the second node n2 are short-circuited. A common mode referencevoltage VM of a successive approximation register analog-to-digitalconverter 150 is applied to a common connection node n10 of the 4aswitch 192 a and the 4b switch 192 b.

The 5a switch 196 a, the positive-side capacitance element 195__(P), thenegative-side capacitance element 195__(M), and the 5b switch 196 b areconnected in series in this order between the first node n1 and thesecond node n2. When the 5a switch 196 a and the 5b switch 196 b are putinto a closed state, the positive-side capacitance element 195__(P) andthe negative-side capacitance element 195__(M) are connected in seriesbetween the first node n1 and the second node n2.

The 5c switch 196 c selectively applies the common mode referencevoltage VM to a common connection node n5 of the positive-sidecapacitance element 195__(P) and the negative-side capacitance element195__(M). When the 5c switch 196 c is put into a closed state, thecommon mode reference voltage VM is applied to the common connectionnode n5.

FIG. 16 is a timing chart of the capacitance unit 19 in FIG. 15 . FIG.16 includes switch control signals RST and SSHT in place of the switchcontrol signal SVMH in FIG. 13 . The switch control signal RST controlson/off of the 4a switch 192 a and the 4b switch 192 b. The switchcontrol signal SSHT controls on/off of the 5a switch 196 a and the 5bswitch 196 b. A switch control signal SREFH controls on/off of the 5cswitch 196 c.

The 4a switch 192 a and the 4b switch 192 b are put into a closed statein a period from time t1 to time t2 and a period from time t3 to timet4. Therefore, the first node n1 and the second node n2 areshort-circuited and the common mode reference voltage VM is applied tothese nodes immediately before a period in which the capacitance unit 19samples a voltage of a signal line VSL and immediately before a periodin which a pixel signal held by the capacitance unit 19 is transferredto the successive approximation register analog-to-digital converter150.

The 5a switch 196 a and the 5b switch 196 b are put into an opened statein the period from time t3 to time t4. Therefore, immediately before theperiod in which the pixel signal held by the capacitance unit 19 istransferred to the successive approximation register analog-to-digitalconverter 150, the connection between the first node n1 and thepositive-side capacitance element 195__(P) is temporarily interrupted,and the connection between the second node n2 and the negative-sidecapacitance element 195__(M) is temporarily interrupted. At that time,the 4a switch 192 a and the 4b switch 192 b are put into a closed state,so that parasitic capacitances Cp1 and Cp2 of the first node n1 and thesecond node n2 are reset by the common mode reference voltage VM.

The 5c switch 196 c is put into a closed state in the period from timet1 to time t2 and a period from time t4 to time t5. Therefore, thecommon mode reference voltage VM is applied to the common connectionnode n5 of the positive-side capacitance element 195__(P) and thenegative-side capacitance element 195__(M) immediately before the periodin which the capacitance unit 19 samples the voltage of the signal lineVSL, and in the period in which the pixel signal held by the capacitanceunit 19 is transferred to the successive approximation registeranalog-to-digital converter 150.

Since the capacitance unit 19 in FIG. 15 includes the 4a switch 192 aand the 4b switch 192 b, it is possible to reset the parasiticcapacitances Cp1 and Cp2 of the first node n1 and the second node n2 toset the first node n1 and the second node n2 to the common modereference voltage VM immediately before the period in which thecapacitance unit 19 samples the voltage of the signal line VSL andimmediately before the period in which the pixel signal held by thecapacitance unit 19 is transferred to the successive approximationregister analog-to-digital converter 150. Therefore, it is possible tosuppress fluctuation of a common voltage of a differential signal due toan influence of the parasitic capacitances Cp1 and Cp2 of the first noden1 and the second node n2, respectively.

Furthermore, in the capacitance unit 19 in FIG. 15 , in a period inwhich the 4a switch 192 a and the 4b switch 192 b are put into a closedstate and the parasitic capacitances of the first node n1 and the secondnode n2 are reset, the 5a switch 196 a and the 5b switch 196 b are putinto an opened state so that charges of the positive-side capacitanceelement 195__(P) and the negative-side capacitance element 195__(M) arenot affected by the parasitic capacitances Cp1 and Cp2 of the first noden1 and the second node n2, respectively.

However, due to an influence of a parasitic capacitance Cp3 of thecommon connection node n5 of the positive-side capacitance element195__(P) and the 5a switch 196 a and a parasitic capacitance Cp4 of thecommon connection node n5 of the negative-side capacitance element195__(M) and the 5b switch 196 b, the common voltage of the differentialsignal transferred from the capacitance unit 19 to the successiveapproximation register analog-to-digital converter 150 has input signaldependency.

FIG. 17 is a diagram illustrating the input signal dependency of thedifferential signal transferred from the capacitance unit 19 to thesuccessive approximation register analog-to-digital converter 150 inFIG. 15 . FIG. 17 illustrates graphs gp1, gp2, and gp3 illustrating theinput signal dependency of differential signals compinp and compinn ofthe nodes n11 and n12, and a common voltage of the differential signals,respectively. As illustrated, in the capacitance unit 19 in FIG. 15 ,the common voltage of the differential signal has the input signaldependency similarly to the capacitance unit 19 in FIG. 12 . Note that,magnitude of the parasitic capacitance may be adjusted by devising eachcircuit element forming the capacitance unit 19, a wiring pattern andthe like. Therefore, even with the capacitance unit 19 having thecircuit configuration in FIG. 15 , the parasitic capacitances Cp3 andCp4 may be reduced.

In this manner, in the capacitance unit 19 in FIG. 15 , by providing the4a switch 192 a, the 4b switch 192 b, the 5a switch 196 a, and the 5bswitch 196 b, the parasitic capacitances Cp1 and Cp2 of the first noden1 and the second node n2 may be reset, and it is possible to preventthe charges in the positive-side capacitance element 195__(P) and thenegative-side capacitance element 195__(M) from being affected by theparasitic capacitances Cp1 and Cp2. However, the common voltage of thedifferential signal transferred from the capacitance unit 19 to thesuccessive approximation register analog-to-digital converter 150 mightfluctuate by the parasitic capacitance Cp3 of the common connection noden5 of the positive-side capacitance element 195__(P) and the 5a switch196 a and the parasitic capacitance Cp4 of the common connection node n5of the negative-side capacitance element 195__(M) and the 5b switch 196b, and a measure for this is hereinafter described.

(Second Variation of Capacitance Unit 19)

FIG. 18 is a circuit diagram illustrating an internal configuration of acapacitance unit 19 according to a second variation of FIG. 12 . Thecapacitance unit 19 in FIG. 18 includes a positive-side capacitanceelement 195__(P), a negative-side capacitance element 195__(M), a 4aswitch 192 a, a 4b switch 192 b, a 5a switch 196 a, a 5b switch 196 b, a5c switch 196 c, a sixth switch 194__(P), a seventh switch 194__(M), aswitch 191__(P), and a switch 191__(M). Hereinafter, a difference fromthe capacitance unit 19 in FIG. 15 is mainly described.

The positive-side capacitance element 195__(P), the 5a switch 196 a, the5b switch 196 b, and the negative-side capacitance element 195__(M) areconnected in series in this order between a first node n1 and a secondnode n2. In this manner, in the capacitance unit 19 in FIG. 18 , theconnection order of the positive-side capacitance element 195__(P) andthe 5a switch 196 a is reversed, and the connection order of thenegative-side capacitance element 195__(M) and the 5b switch 196 b isreversed from those of the capacitance unit 19 in FIG. 15 .

FIG. 19 is a timing chart of the capacitance unit 19 in FIG. 18 . As maybe seen by comparing FIG. 19 with FIG. 16 , the capacitance unit 19 inFIG. 18 operates at the same timing as that of the capacitance unit 19in FIG. 15 , but performs a different circuit operation by reversing theconnection order of the positive-side capacitance element 195__(P) andthe 5a switch 196 a and reversing the connection order of thenegative-side capacitance element 195__(M) and the 5b switch 196 b.

In a period (time t3 to time t4) in which the 4a switch 192 a and the 4bswitch 192 b are put into a closed state and parasitic capacitances Cp1and Cp2 of the first node n1 and the second node n2 are reset, the 5aswitch 196 a and the 5b switch 196 b are put into an opened state.Therefore, pixel signals held by the positive-side capacitance element195__(P) and the negative-side capacitance element 195__(M) are notaffected by the parasitic capacitances Cp1 and Cp2 of the first node n1and the second node n2.

Furthermore, since the 5a switch 196 a, the 5b switch 196 b, and the 5cswitch 196 c are put into a closed state in the period from time t1 totime t2, parasitic capacitances Cp3, Cp4, and Cp7 of a common connectionnode n3 of the positive-side capacitance element 195__(P) and the 5aswitch 196 a, a common connection node n4 of the negative-sidecapacitance element 195__(M) and the 5b switch 196 b, and a commonconnection node n5 of the 5a switch 196 a and the 5b switch 196 b may bereset, and these nodes n3 to n5 may be set to a common mode referencevoltage VM.

FIG. 20 is a diagram illustrating the input signal dependency of thedifferential signal transferred from the capacitance unit 19 to thesuccessive approximation register analog-to-digital converter 150 inFIG. 18 . FIG. 20 illustrates graphs gp1, gp2, and gp3 illustrating theinput signal dependency of differential signals compinp and compinn ofthe nodes n11 and n12, and a common voltage of the differential signals,respectively.

The capacitance unit 19 in FIG. 18 resets the parasitic capacitancesCp3, Cp4, and Cp7 by putting the 5a switch 196 a, the 5b switch 196 b,and the 5c switch 196 c into a closed state, so that the input signaldependency of the common voltage common of the differential signal maybe made smaller than that of the capacitance unit 19 in FIG. 15 .

(Third Variation of Capacitance Unit 19)

In the capacitance unit 19 in FIGS. 15 and 18 described above, the resetof the positive-side capacitance element 195P and the negative-sidecapacitance element 195__(M) and the reset of the parasitic capacitanceare performed at different timings, but these operations may becollectively performed.

FIG. 21 is a circuit diagram illustrating an internal configuration of acapacitance unit 19 according to a third variation of FIG. 12 . Thecapacitance unit 19 in FIG. 21 includes a positive-side capacitanceelement 195__(P), a negative-side capacitance element 195__(M), a 4aswitch 192 a, a 4b switch 192 b, a 4c switch 192 c, a 5a switch 196 a, a5b switch 196 b, a 5c switch 196 c, a sixth switch 194__(P), a seventhswitch 194__(M), a switch 191__(P), and a switch 191__(M). Hereinafter,a difference from the capacitance unit 19 in FIG. 18 is mainlydescribed.

The positive-side capacitance element 195__(P) in FIG. 21 is connectedbetween a first node n1 and a third node n3. The negative-sidecapacitance element 195__(M) is connected between a second node n2 and afourth node n4. A pixel signal from the column amplifier 140 is suppliedto the first node n1. A reference voltage VR is supplied to the secondnode n2.

The 4a switch 192 a and the 4b switch 192 b are connected in seriesbetween the first node n1 and the second node n2. When the 4a switch 192a and the 4b switch 192 b are put into a closed state, the first node n1and the second node n2 are short-circuited, and a common mode referencevoltage VM is applied to the nodes.

The 4c switch 192 c is connected between the first node n1 and thesecond node n2. When the 4c switch 192 c is put into a closed state, thefirst node n1 and the second node n2 are short-circuited.

The 5a switch 196 a is connected between the third node n3 and thefourth node n4. When the 5a switch 196 a is put into a closed state, thethird node n3 and the fourth node n4 are short-circuited.

The 5b switch 196 b and the 5c switch 196 c are connected in seriesbetween the third node n3 and the fourth node n4. When the 5b switch 196b and the 5c switch 196 c are put into a closed state, the 5b switch 196b and the 5c switch 196 c are short-circuited, and the common modereference voltage VM is applied to these nodes.

FIG. 22 is a timing chart of the capacitance unit 19 in FIG. 21 . Aswitch control signal RST controls on/off of the 4c switch 192 c, the 5bswitch 196 b, and the 5c switch 196 c. A switch control signal SVMHcontrols on/off of the 5a switch 196 a. A switch control signal SREFHcontrols on/off of the 4a switch 192 a and the 4b switch 192 b.

The 4c switch 192 c, the 5b switch 196 b, and the 5c switch 196 c areput into a closed state in a period from time t1 to time t2. When the 4cswitch 192 c is put into a closed state, the first node n1 and thesecond node n2 are short-circuited. When the 5b switch 196 b and the 5cswitch 196 c are put into a closed state, the third node n3 and thefourth node n4 are short-circuited, and the common mode referencevoltage VM is applied. Therefore, a parasitic capacitance Cp3 of thethird node n3 and a parasitic capacitance Cp4 of the fourth node n4 arereset.

The 5a switch 196 a is put into a closed state in a period from time t2to time t3, and when the 5a switch 196 a is put into a closed state, thethird node n3 and the fourth node n4 are short-circuited.

The 4a switch 192 a and the 4b switch 192 b are put into a closed statein a period from time t4 to time t5, and when the 4a switch 192 a andthe 4b switch 192 b are put into a closed state, the first node n1 andthe second node n2 are short-circuited and the common mode referencevoltage VM is applied.

In the capacitance unit 19 in FIG. 21 , the input and output of thepositive-side capacitance element 195__(P) are set to the first node n1and the third node n3, the input and output of the negative-sidecapacitance element 195__(M) are set to the second node n2 and thefourth node n4, and the positive-side capacitance element 195__(P) andthe negative-side capacitance element 195__(M) are separately providedwith input and output nodes. Since the reference voltage VR is suppliedto the first node n1 and the second node n2 immediately before a periodin which the capacitance unit 19 samples a voltage of a signal line VSL,parasitic capacitances Cp1 and Cp2 of the first node n1 and the secondnode n2 are automatically reset. Therefore, an operation of resettingthe parasitic capacitances Cp1 and Cp2 becomes unnecessary.

FIG. 23 is a diagram illustrating the input signal dependency of thedifferential signal transferred from the capacitance unit 19 to thesuccessive approximation register analog-to-digital converter 150 inFIG. 21 . FIG. 23 illustrates graphs gp1, gp2, and gp3 illustrating theinput signal dependency of differential signals compinp and compinn ofthe nodes n11 and n12, and a common voltage of the differential signals,respectively.

Since the capacitance unit 19 in FIG. 21 sets the input and output ofthe positive-side capacitance element 195__(P) and the negative-sidecapacitance element 195__(M) to separate nodes, it is possible to resetthe parasitic capacitances Cp1 and Cp2 of the first node n1 and thesecond node n2 immediately before the period in which the capacitanceunit 19 samples the voltage of the signal line VSL, and it is possiblethat the parasitic capacitances Cp3 and Cp4 of the third node n3 and thefourth node n4 are not reset immediately before a period in which thepixel signal held by the capacitance unit 19 is transferred to thesuccessive approximation register analog-to-digital converter 150.Furthermore, input signal dependency of the common voltage of thedifferential signal may also be reduced.

(Fourth Variation of Capacitance Unit 19)

Each of the capacitance units 19 described above uses the common modereference voltage VM when transferring the pixel signal from thecapacitance unit 19 to the successive approximation registeranalog-to-digital converter 150. Since the common mode reference voltageVM is commonly used in all the columns, when the common mode referencevoltage VM fluctuates at the time of AD conversion in another column,there might be an influence. Therefore, it is also conceivable not touse the common mode reference voltage VM at the time of transfer of thepixel signal.

FIG. 24 is a circuit diagram illustrating an internal configuration of acapacitance unit 19 according to a fourth variation of FIG. 12 . Thecapacitance unit 19 in FIG. 24 includes a positive-side capacitanceelement 195__(P), a negative-side capacitance element 195__(M), a fourthswitch 192, a 5a switch 196 a, a 5b switch 196 b, a 5c switch 196 c, asixth switch 194__(P), a seventh switch 194__(M), a switch 191__(P), anda switch 191__(M). Hereinafter, a difference from the capacitance unit19 in FIG. 21 is mainly described.

The fourth switch 192 is connected between a first node n1 and a secondnode n2. When the fourth switch 192 is put into a closed state, thefirst node n1 and the second node n2 are short-circuited.

The 5a switch 196 a and the 5b switch 196 b are connected in seriesbetween a third node n3 and a fourth node n4. When the 5a switch 196 aand the 5b switch 196 b are put into a closed state, the third node n3and the fourth node n4 are short-circuited.

The 5c switch 196 c selectively applies the common mode referencevoltage VM of the successive approximation register analog-to-digitalconverter 150 to a common connection node n5 of the 5a switch 196 a andthe 5b switch 196 b. When the 5c switch 196 c is put into a closedstate, the common mode reference voltage VM is applied to the commonconnection node n5.

FIG. 25 is a timing chart of the capacitance unit 19 in FIG. 24 . Aswitch control signal SVMH controls on/off of the 5a switch 196 a andthe 5b switch 196 b. A switch control signal SREFH controls on/off ofthe fourth switch 192.

The fourth switch 192 is put into a closed state in the period from timet1 to time t2. Therefore, the first node n1 and the second node n2 areshort-circuited immediately before a period in which the capacitanceunit 19 samples a voltage of a signal line VSL.

Furthermore, the 5a switch 196 a and the 5b switch 196 b are put into aclosed state in a period from time t1 to time t3, and the 5c switch 196c is put into a closed state in a period from time t1 to time t2.Therefore, the third node n3 and the fourth node n4 are short-circuitedimmediately before the period in which the capacitance unit 19 samplesthe voltage of the signal line VSL, and the common mode referencevoltage VM is applied. Therefore, parasitic capacitances Cp3, Cp4, andCp1 of the third node n3, the fourth node n4, and the common connectionnode n5, respectively, are reset.

In contrast, the common mode reference voltage VM is not applied to thethird node n3 and the fourth node n4 immediately before (t3 to t4) aperiod in which the pixel signal held by the capacitance unit 19 istransferred to the successive approximation register analog-to-digitalconverter 150. Therefore, even if the common mode reference voltage VMfluctuates due to AD conversion of another column, there is noinfluence. However, by the influence of the parasitic capacitances Cp1and Cp2 of the first node n1 and the second node n2, the common voltageof the differential signal transferred to the successive approximationregister analog-to-digital converter might fluctuate.

FIG. 26 is a diagram illustrating the input signal dependency of thedifferential signal transferred from the capacitance unit 19 to thesuccessive approximation register analog-to-digital converter 150 inFIG. 24 . FIG. 26 illustrates graphs gp1, gp2, and gp3 illustrating theinput signal dependency of differential signals compinp and compinn ofthe nodes n11 and n12, and a common voltage of the differential signals,respectively.

In the capacitance unit 19 in FIG. 24 , when transferring the pixelsignal to the successive approximation register analog-to-digitalconverter 150, the common voltage of the differential signal transferredto the successive approximation register analog-to-digital converter 150might fluctuate by the influence of the parasitic capacitances Cp1 andCp2 of the first node n1 and the second node n2. A measure for this ishereinafter described.

(Fifth Variation of Capacitance Unit 19)

FIG. 27 is a circuit diagram illustrating an internal configuration of acapacitance unit 19 according to a fifth variation of FIG. 12 . Thecapacitance unit 19 in FIG. 27 includes a positive-side capacitanceelement 195__(P), a negative-side capacitance element 195__(M), a 4aswitch 192 a, a 4b switch 192 b, a 4c switch 192 c, a 5a switch 196 a, a5b switch 196 b, a 5c switch 196 c, a sixth switch 194__(P), a seventhswitch 194__(M), a switch 191__(P), and a switch 191__(M).

The 4a switch 192 a and the 4b switch 192 b are connected in seriesbetween a first node n1 and a second node n2. When the 4a switch 192 aand the 4b switch 192 b are put into a closed state, the first node n1and the second node n2 are short-circuited.

The 4c switch 192 c selectively applies a reference voltage VR to acommon connection node n10 of the 4a switch 192 a and the 4b switch 192b. When the 4c switch 192 c is put into a closed state, the referencevoltage VR is applied to the common connection node n10.

The 5a switch 196 a and the 5b switch 196 b are connected in seriesbetween a third node n3 and a fourth node n4. When the 5a switch 196 aand the 5b switch 196 b are put into a closed state, the third node n3and the fourth node n4 are short-circuited.

The 5c switch 196 c selectively applies the common mode referencevoltage VM of the successive approximation register analog-to-digitalconverter 150 to a common connection node n5 of the 5a switch 196 a andthe 5b switch 196 b. When the 5c switch 196 c is put into a closedstate, the common mode reference voltage VM is applied to the commonconnection node n5.

FIG. 28 is a timing chart of the capacitance unit 19 in FIG. 27 . Aswitch control signal RST1 controls on/off of the 5c switch 196 c. Aswitch control signal RST2 controls on/off of the 4c switch 192 c. Aswitch control signal SVHM controls on/off of the 5a switch 196 a andthe 5b switch 196 b. A switch control signal SREFH controls on/off ofthe 4a switch 192 a and the 4b switch 192 b.

The 4a switch 192 a, the 4b switch 192 b, and the 4c switch 192 c areput into a closed state in a period from time t1 to time t2. Therefore,the first node n1 and the second node n2 are short-circuited immediatelybefore a period in which the capacitance unit 19 samples a voltage of asignal line VSL, and the reference voltage VR is applied to these nodes.

Furthermore, the 5a switch 196 a, the 5b switch 196 b, and the 5c switch196 c are put into a closed state in a period from time t1 to time t2.Therefore, the third node n3 and the fourth node n4 are short-circuitedimmediately before the period in which the capacitance unit 19 samplesthe voltage of the signal line VSL, and the common mode referencevoltage VM is applied to these nodes.

Therefore, immediately before the period in which the capacitance unit19 samples the voltage of the signal line VSL, a parasitic capacitanceCp1 of the first node n1, a parasitic capacitance Cp2 of the second noden2, a parasitic capacitance Cp8 of the common connection node n10 of the4a switch 192 a and the 4b switch 192 b, a parasitic capacitance Cp3 ofthe third node n3, a parasitic capacitance Cp4 of the fourth node n4,and a parasitic capacitance Cp1 of the common connection node n5 of the5a switch 196 a and the 5b switch 196 b are reset.

Furthermore, the 4a switch 192 a, the 4b switch 192 b, and the 4c switch192 c are put into a closed state in a period from time t3 to time t4.Therefore, immediately before a period in which a pixel signal held bythe capacitance unit 19 is transferred to the successive approximationregister analog-to-digital converter 150, the first node n1 and thesecond node n2 are short-circuited, the reference voltage VR is appliedto these nodes, and the parasitic capacitances Cp1, Cp2, and Cp8described above are reset.

In contrast, in the period from time t3 to time t4, the 5c switch 196 cis in an opened state, and the common mode reference voltage VM is notapplied to the third node n3 and the fourth node n4; however, the 5aswitch 196 a and the 5b switch are put into a closed state, so that thethird node n3 and the fourth node n4 are short-circuited, and theparasitic capacitances Cp3 and Cp4 are reset. Therefore, fluctuation ofthe common voltage in the period in which the pixel signal held by thecapacitance unit 19 is transferred to the successive approximationregister analog-to-digital converter 150 may be suppressed.

FIG. 29 is a diagram illustrating the input signal dependency of thedifferential signal transferred from the capacitance unit 19 to thesuccessive approximation register analog-to-digital converter 150 inFIG. 27 . FIG. 26 illustrates graphs gp1, gp2, and gp3 illustrating theinput signal dependency of differential signals compinp and compinn ofthe nodes n11 and n12, and a common voltage of the differential signals,respectively.

Since the capacitance unit 19 in FIG. 27 does not use the common modereference voltage VM when transferring the pixel signal to thesuccessive approximation register analog-to-digital converter 150, thisis not affected by AD conversion of other columns, and since theparasitic capacitances Cp1 and Cp2 of the first node n1 and the secondnode n2 are reset before the pixel signal is transferred to thesuccessive approximation register analog-to-digital converter 150, theinput signal dependency of the common voltage of the differential signalmay be reduced.

<Second Embodiment of Present Disclosure>

A second embodiment of the present disclosure is an example in which thetechnology according to the present disclosure is applied to an indirecttime-of-flight (TOF) distance image sensor. The indirect TOF distanceimage sensor is a sensor that measures a distance to a measurementtarget by measuring a light flight time on the basis of detection of anarrival phase difference of reflected light, the light emitted from alight source and reflected by the measurement target (subject).

[System Configuration Example]

FIG. 30 is a block diagram illustrating an example of a systemconfiguration of the indirect TOF distance image sensor according to thesecond embodiment of the present disclosure.

On an indirect TOF distance image sensor 50, reflected light, the lightemitted from a light source 60 and reflected by a measurement target(subject) is incident. The indirect TOF distance image sensor 50 has astacked structure including a sensor chip 51 and a circuit chip 52stacked on the sensor chip 51. In this stacked structure, the sensorchip 51 and the circuit chip 52 are electrically connected to each othervia a connection (not illustrated) such as a via (VIA) or Cu—Cuconnection. Note that, FIG. 30 illustrates a state in which wiring ofthe sensor chip 51 and wiring of the circuit chip 52 are electricallyconnected to each other via the connection described above.

A pixel array unit 53 is formed on the sensor chip 51. The pixel arrayunit 53 includes a plurality of pixels 54 arranged in a matrix (array)in a two-dimensional grid pattern on the sensor chip 51. In the pixelarray unit 53, each of the plurality of pixels 54 receives incidentlight (for example, near infrared light), performs photoelectricconversion, and outputs an analog pixel signal. In the pixel array unit53, two signal lines VSL₁ and VSL₂ are wired for each pixel column. Whenthe number of pixel columns of the pixel array unit 53 is set to M (M isan integer), a total of (2×M) signal lines VSL are wired in the pixelarray unit 53.

Each of the plurality of pixels 54 includes first and second taps A andB (details thereof are to be described later). An analog pixel signalAIN_(P1) based on a charge of the first tap A of the pixel 54 in thecorresponding pixel column is output to the signal line VSL₁ out of thetwo signal lines VSL₁ and VSL₂. Furthermore, an analog pixel signalAIN_(P2) based on a charge of the second tap B of the pixel 54 in thecorresponding pixel column is output to the signal line VSL₂. The analogpixel signals AIN_(P1) and AIN_(P2) are to be described later.

On the circuit chip 52, a row selection unit 55, a column signalprocessing unit 56, an output circuit unit 57, and a timing control unit58 are arranged. The row selection unit 55 drives the respective pixels54 of the pixel array unit 53 in units of pixel row to output the pixelsignals AIN_(P1) and AIN_(P2), respectively. Under the drive by the rowselection unit 55, the analog pixel signals AIN_(P1) and AIN_(P2) outputfrom the pixels 54 in the selected row are supplied to the column signalprocessing unit 56 via the two signal lines VSL₁ and VSL₂.

The column signal processing unit 56 includes a plurality ofanalog-to-digital converters (ADC) 59 provided corresponding to thepixel columns of the pixel array unit 53 (for example, for each pixelcolumn). The analog-to-digital converter 59 performs analog-to-digitalconversion processing on the analog pixel signals AIN_(P1) and AIN_(P2)supplied via the signal lines VSL₁ and VSL₂, respectively, to output tothe output circuit unit 57. The output circuit unit 57 performspredetermined signal processing on the digitized pixel signals AIN_(P1)and AIN_(P2) output from the column signal processing unit 56 to outputout of the circuit chip 52.

The timing control unit 58 generates various timing signals, clocksignals, control signals and the like, and performs drive control of therow selection unit 55, the column signal processing unit 56, the outputcircuit unit 57 and the like on the basis of the signals.

[Circuit Configuration Example of Pixel]

FIG. 31 is a circuit diagram illustrating an example of a circuitconfiguration of the pixel 54 in the indirect TOF distance image sensor50 according to the second embodiment.

The pixel 54 according to this example includes, for example, aphotodiode 541 as a photoelectric conversion element. The pixel 54includes, in addition to the photodiode 541, an overflow transistor 542,two transfer transistors 543 and 544, two reset transistors 545 and 546,two floating diffusion layers 547 and 548, two amplification transistors549 and 550, and two selection transistors 551 and 552. The two floatingdiffusion layers 547 and 548 correspond to the first and second taps Aand B (hereinafter, sometimes simply referred to as “taps A and B”)illustrated in FIG. 30 .

The photodiode 541 generates a charge by photoelectrically convertingthe received light. The photodiode 541 may have, for example, aback-illuminated pixel structure. However, the structure is not limitedto the back-illuminated structure, and may be a front-illuminatedstructure that captures light applied from a substrate front surfaceside.

The overflow transistor 542 is connected between a cathode electrode ofthe photodiode 541 and a power supply line of a power supply voltageV_(DD), and has a function of resetting the photodiode 541.Specifically, the overflow transistor 542 becomes conductive in responseto an overflow gate signal TRG supplied from the row selection unit 55,thereby sequentially transferring the charge generated by the photodiode541 to the floating diffusion layers 547 and 548.

The floating diffusion layers 547 and 548 corresponding to the first andsecond taps A and B, accumulate the charge transferred from thephotodiode 541, convert the same into a voltage signal having a voltagevalue corresponding to a charge amount, and generate the pixel signalsAIN_(P1) and AIN_(P2), respectively.

Each of the two reset transistors 545 and 546 is connected between eachof the two floating diffusion layers 547 and 548 and the power supplyline of the power supply voltage V_(DD). Then, each of the resettransistor 545 and 546 becomes conductive in response to a reset signalRST supplied from the row selection unit 55, thereby extracting thecharge from each of the floating diffusion layers 347 and 348 andinitializing the charge amount.

Each of the two amplification transistors 549 and 550 is connectedbetween each of the power supply line of the power supply voltage V_(DD)and each of the two selection transistors 551 and 552, and amplifies avoltage signal converted from the charge to a voltage in each of thefloating diffusion layers 547 and 548.

The two selection transistors 551 and 552 are connected between each ofthe two amplification transistors 549 and 550 and each of the signallines VSL₁ and VSL₂, respectively. Then, the selection transistors 551and 552 become conductive in response to a selection signal SEL suppliedfrom the row selection unit 55, thereby outputting the voltage signalsamplified by the amplification transistors 549 and 550 to the two signallines VSL₁ and VSL₂ as analog pixel signals AIN_(P1) and AIN_(P2),respectively.

The two signal lines VSL₁ and VSL₂ are connected to an input end of oneanalog-to-digital converter 59 in the column signal processing unit 56for each pixel column, and transmit the analog pixel signals AIN_(P1)and AIN_(P2) output from the pixels 54 for each pixel column to theanalog-to-digital converter 59.

Note that, the circuit configuration of the pixel 54 is not limited tothe circuit configuration illustrated in FIG. 31 as long as the circuitconfiguration may generate the analog pixel signals AIN_(P1) andAIN_(P2) by the photoelectric conversion.

In the indirect TOF distance image sensor 50 having the configurationdescribed above, the technology according to the present disclosure maybe applied to the column signal processing unit 56 including theanalog-to-digital converter 59. More specifically, as the column signalprocessing unit 56 including the analog-to-digital converter 59,similarly to a case of the first embodiment, the column signalprocessing system according to the first embodiment or Example 4including the column amplifier unit 14, the capacitance unit 19, and thesuccessive approximation register analog-to-digital conversion unit 15Amay be used.

<Variation>

Although the technology according to the present disclosure is describedabove on the basis of the preferred embodiments, the technologyaccording to the present disclosure is not limited to the embodiments.The configurations and structures of the CMOS image sensor and theindirect TOF distance image sensor described in the embodimentsdescribed above are examples, and may be changed as appropriate.

Application Example

The imaging device (CMOS image sensor) according to the first embodimentmay be used in various devices in which light such as visible light,infrared light, ultraviolet light, and X-ray is sensed as illustrated inFIG. 32 , for example. Specific examples of the various devices arelisted below.

-   -   A device that takes an image to be used for viewing such as a        digital camera and a mobile device with a camera function    -   A device for traffic purpose such as a vehicle-mounted sensor        that takes images of the front, rear, surroundings, interior and        the like of an automobile, a monitoring camera that monitors        traveling vehicles and roads, and a ranging sensor that measures        a distance between vehicles and the like for safe driving such        as automatic stop, recognition of a driver's condition and the        like    -   A device for home appliance such as a television, a        refrigerator, and an air conditioner that takes an image of a        user's gesture and performs a device operation according to the        gesture    -   A device for medical and health care use such as an endoscope        and a device that performs angiography by receiving infrared        light    -   A device for security use such as a security monitoring camera        and an individual certification camera    -   A device for beauty care such as a skin condition measuring        device that takes an image of skin and a microscope that takes        an image of scalp    -   A device for sporting use such as an action camera and a        wearable camera for sporting use and the like    -   A device for agricultural use such as a camera for monitoring        land and crop states        <Application Example of Technology according to Present        Disclosure>

The technology according to the present disclosure may be applied tovarious products. A more specific application example is describedbelow.

[Electronic Device of Present Disclosure]

Here, a case of applying to an imaging system such as a digital stillcamera or a video camera, a mobile terminal device having an imagingfunction such as a mobile phone, or an electronic device such as acopier using an imaging device as an image read unit is described.

(Example of Imaging System)

FIG. 33 is a block diagram illustrating a configuration example of animaging system as an example of an electronic device of the presentdisclosure.

As illustrated in FIG. 33 , an imaging system 100 according to thisexample includes an imaging optical system 101 including a lens groupand the like, an imaging unit 102, a digital signal processor (DSP)circuit 103, a frame memory 104, a display device 105, a recordingdevice 106, an operation system 107, a power supply system 108 and thelike. Then, the DSP circuit 103, the frame memory 104, the displaydevice 105, the recording device 106, the operation system 107, and thepower supply system 108 are connected to one another via a bus line 109.

The imaging optical system 101 captures incident light (image light)from a subject to form an image on an imaging surface of the imagingunit 102. The imaging unit 102 converts a light amount of the incidentlight the image of which is formed on the imaging surface thereof by theoptical system 101 to an electric signal in units of pixel to output asa pixel signal. The DSP circuit 103 performs general camera signalprocessing, for example, white balance processing, demosaic processing,gamma correction processing and the like.

The frame memory 104 is appropriately used for storing data in theprocess of signal processing in the DSP circuit 103. The display device105 including a panel display device such as a liquid crystal displaydevice and an organic electro luminescence (EL) display device displaysa moving image or a still image taken by the imaging unit 102. Therecording device 106 records the moving image or the still image takenby the imaging unit 102 on a recording medium such as a portablesemiconductor memory, an optical disk, or a hard disk drive (HDD).

The operation system 107 issues an operation command regarding variousfunctions of the imaging system 100 under an operation by a user. Thepower supply system 108 appropriately supplies various power suppliesserving as operation power supplies of the DSP circuit 103, the framememory 104, the display device 105, the recording device 106, and theoperation system 107 to supply targets.

In the imaging system 100 having the configuration described above, theimaging device according to the first embodiment described above may beused as the imaging unit 102. In the imaging device according to thefirst embodiment, in particular, the successive approximation registeranalog-to-digital converter 150 is excellent in power efficiency, sothat it is possible to contribute to low power consumption of theimaging system 100 by using the imaging device as the imaging unit 102.

[Application Example to Mobile Body]

The technology according to the present disclosure (present technology)may be applied to various products. For example, the technologyaccording to the present disclosure may also be implemented as animaging device mounted on any type of mobile body such as an automobile,an electric automobile, a hybrid electric automobile, a motorcycle, abicycle, a personal mobility, an airplane, a drone, a ship, a robot, abuilding machine, or an agricultural machine (tractor).

FIG. 34 is a block diagram depicting an example of schematicconfiguration of a vehicle control system as an example of a mobile bodycontrol system to which the technology according to an embodiment of thepresent disclosure can be applied.

The vehicle control system 12000 includes a plurality of electroniccontrol units connected to each other via a communication network 12001.In the example depicted in FIG. 34 , the vehicle control system 12000includes a driving system control unit 12010, a body system control unit12020, an outside-vehicle information detecting unit 12030, anin-vehicle information detecting unit 12040, and an integrated controlunit 12050. Furthermore, a microcomputer 12051, a sound/image outputsection 12052, and a vehicle-mounted network interface (I/F) 12053 areillustrated as a functional configuration of the integrated control unit12050.

The driving system control unit 12010 controls the operation of devicesrelated to the driving system of the vehicle in accordance with variouskinds of programs. For example, the driving system control unit 12010functions as a control device for a driving force generating device forgenerating the driving force of the vehicle, such as an internalcombustion engine, a driving motor, or the like, a driving forcetransmitting mechanism for transmitting the driving force to wheels, asteering mechanism for adjusting the steering angle of the vehicle, abraking device for generating the braking force of the vehicle, and thelike.

The body system control unit 12020 controls the operation of variouskinds of devices provided to a vehicle body in accordance with variouskinds of programs. For example, the body system control unit 12020functions as a control device for a keyless entry system, a smart keysystem, a power window device, or various kinds of lamps such as aheadlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or thelike. In this case, radio waves transmitted from a mobile device as analternative to a key or signals of various kinds of switches can beinput to the body system control unit 12020. The body system controlunit 12020 receives these input radio waves or signals, and controls adoor lock device, the power window device, the lamps, or the like of thevehicle.

The outside-vehicle information detecting unit 12030 detects informationabout the outside of the vehicle including the vehicle control system12000. For example, the outside-vehicle information detecting unit 12030is connected with an imaging section 12031. The outside-vehicleinformation detecting unit 12030 makes the imaging section 12031 imagean image of the outside of the vehicle, and receives the imaged image.On the basis of the received image, the outside-vehicle informationdetecting unit 12030 may perform processing of detecting an object suchas a human, a vehicle, an obstacle, a sign, a character on a roadsurface, or the like, or processing of detecting a distance thereto.

The imaging section 12031 is an optical sensor that receives light, andwhich outputs an electric signal corresponding to a received lightamount of the light. The imaging section 12031 can output the electricsignal as an image, or can output the electric signal as informationabout a measured distance. In addition, the light received by theimaging section 12031 may be visible light, or may be invisible lightsuch as infrared rays or the like.

The in-vehicle information detecting unit 12040 detects informationabout the inside of the vehicle. The in-vehicle information detectingunit 12040 is, for example, connected with a driver state detectingsection 12041 that detects the state of a driver. The driver statedetecting section 12041, for example, includes a camera that images thedriver. On the basis of detection information input from the driverstate detecting section 12041, the in-vehicle information detecting unit12040 may calculate a degree of fatigue of the driver or a degree ofconcentration of the driver, or may determine whether the driver isdozing.

The microcomputer 12051 can calculate a control target value for thedriving force generating device, the steering mechanism, or the brakingdevice on the basis of the information about the inside or outside ofthe vehicle which information is obtained by the outside-vehicleinformation detecting unit 12030 or the in-vehicle information detectingunit 12040, and output a control command to the driving system controlunit 12010. For example, the microcomputer 12051 can perform cooperativecontrol intended to implement functions of an advanced driver assistancesystem (ADAS) which functions include collision avoidance or shockmitigation for the vehicle, following driving based on a followingdistance, vehicle speed maintaining driving, a warning of collision ofthe vehicle, a warning of deviation of the vehicle from a lane, or thelike.

In addition, the microcomputer 12051 can perform cooperative controlintended for automated driving, which makes the vehicle to travelautomatedly without depending on the operation of the driver, or thelike, by controlling the driving force generating device, the steeringmechanism, the braking device, or the like on the basis of theinformation about the outside or inside of the vehicle which informationis obtained by the outside-vehicle information detecting unit 12030 orthe in-vehicle information detecting unit 12040.

Furthermore, the microcomputer 12051 can output a control command to thebody system control unit 12020 on the basis of the information about theoutside of the vehicle obtained by the outside-vehicle informationdetecting unit 12030. For example, the microcomputer 12051 can performcooperative control intended to prevent a glare by controlling theheadlamp so as to change from a high beam to a low beam, for example, inaccordance with the position of a preceding vehicle or an oncomingvehicle detected by the outside-vehicle information detecting unit12030.

The sound/image output section 12052 transmits an output signal of atleast one of a sound and an image to an output device capable ofvisually or auditorily notifying information to an occupant of thevehicle or the outside of the vehicle. In the example of FIG. 34 , anaudio speaker 12061, a display section 12062, and an instrument panel12063 are illustrated as the output device. The display section 12062may, for example, include at least one of an on-board display and ahead-up display.

FIG. 35 is a diagram depicting an example of an installation position ofthe imaging section 12031.

In FIG. 35 , a vehicle 12100 includes imaging sections 12101, 12102,12103, 12104, and 12105 as the imaging section 12031.

The imaging sections 12101, 12102, 12103, 12104, and 12105 are, forexample, disposed at positions on a front nose, sideview mirrors, a rearbumper, and a back door of the vehicle 12100 as well as a position on anupper portion of a windshield within the interior of the vehicle. Theimaging section 12101 provided to the front nose and the imaging section12105 provided to the upper portion of the windshield within theinterior of the vehicle obtain mainly an image of the front of thevehicle 12100. The imaging sections 12102 and 12103 provided to thesideview mirrors obtain mainly an image of the sides of the vehicle12100. The imaging section 12104 provided to the rear bumper or the backdoor obtains mainly an image of the rear of the vehicle 12100. Theimages of the front obtained by the imaging sections 12101 and 12105 areused mainly to detect a preceding vehicle, a pedestrian, an obstacle, asignal, a traffic sign, a lane, or the like.

Note that, FIG. 35 depicts an example of imaging ranges of the imagingsections 12101 to 12104. An imaging range 12111 represents the imagingrange of the imaging section 12101 provided to the front nose. Imagingranges 12112 and 12113 respectively represent the imaging ranges of theimaging sections 12102 and 12103 provided to the sideview mirrors. Animaging range 12114 represents the imaging range of the imaging section12104 provided to the rear bumper or the back door. A bird's-eye imageof the vehicle 12100 as viewed from above is obtained by superimposingimage data imaged by the imaging sections 12101 to 12104, for example.

At least one of the imaging sections 12101 to 12104 may have a functionof obtaining distance information. For example, at least one of theimaging sections 12101 to 12104 may be a stereo camera constituted of aplurality of imaging devices, or may be an imaging device having pixelsfor phase difference detection.

For example, the microcomputer 12051 can determine a distance to eachthree-dimensional object within the imaging ranges 12111 to 12114 and atemporal change in the distance (relative speed with respect to thevehicle 12100) on the basis of the distance information obtained fromthe imaging sections 12101 to 12104, and thereby extract, as a precedingvehicle, a nearest three-dimensional object in particular that ispresent on a traveling path of the vehicle 12100 and which travels insubstantially the same direction as the vehicle 12100 at a predeterminedspeed (for example, equal to or more than 0 km/hour). Further, themicrocomputer 12051 can set a following distance to be maintained infront of a preceding vehicle in advance, and perform automatic brakecontrol (including following stop control), automatic accelerationcontrol (including following start control), or the like. It is thuspossible to perform cooperative control intended for automated drivingthat makes the vehicle travel automatedly without depending on theoperation of the driver or the like.

For example, the microcomputer 12051 can classify three-dimensionalobject data on three-dimensional objects into three-dimensional objectdata of a two-wheeled vehicle, a standard-sized vehicle, a large-sizedvehicle, a pedestrian, a utility pole, and other three-dimensionalobjects on the basis of the distance information obtained from theimaging sections 12101 to 12104, extract the classifiedthree-dimensional object data, and use the extracted three-dimensionalobject data for automatic avoidance of an obstacle. For example, themicrocomputer 12051 identifies obstacles around the vehicle 12100 asobstacles that the driver of the vehicle 12100 can recognize visuallyand obstacles that are difficult for the driver of the vehicle 12100 torecognize visually. Then, the microcomputer 12051 determines a collisionrisk indicating a risk of collision with each obstacle. In a situationin which the collision risk is equal to or higher than a set value andthere is thus a possibility of collision, the microcomputer 12051outputs a warning to the driver via the audio speaker 12061 or thedisplay section 12062, and performs forced deceleration or avoidancesteering via the driving system control unit 12010. The microcomputer12051 can thereby assist in driving to avoid collision.

At least one of the imaging sections 12101 to 12104 may be an infraredcamera that detects infrared rays. The microcomputer 12051 can, forexample, recognize a pedestrian by determining whether or not there is apedestrian in imaged images of the imaging sections 12101 to 12104. Suchrecognition of a pedestrian is, for example, performed by a procedure ofextracting characteristic points in the imaged images of the imagingsections 12101 to 12104 as infrared cameras and a procedure ofdetermining whether or not it is the pedestrian by performing patternmatching processing on a series of characteristic points representingthe contour of the object. When the microcomputer 12051 determines thatthere is a pedestrian in the imaged images of the imaging sections 12101to 12104, and thus recognizes the pedestrian, the sound/image outputsection 12052 controls the display section 12062 so that a squarecontour line for emphasis is displayed so as to be superimposed on therecognized pedestrian. The sound/image output section 12052 may alsocontrol the display section 12062 so that an icon or the likerepresenting the pedestrian is displayed at a desired position.

An example of the vehicle control system to which the technologyaccording to the present disclosure is applicable is described above.The technology according to the present disclosure is applicable to, forexample, imaging sections 7910, 7912, 7914, 7916, and 7918 andoutside-vehicle information detecting sections 7920, 7922, 7924, 7926,7928, and 7930 out of the configurations described above. Then, inparticular, the successive approximation register analog-to-digitalconverter 150 is excellent in power efficiency, so that it is possibleto contribute to low power consumption of the vehicle control system byapplying the technology according to the present disclosure.

<Configuration that Present Disclosure may Take>

Note that, the present disclosure may also take a followingconfiguration.

<<A. Imaging Device>>

[A-01] An imaging device provided with:

a pixel array unit including a plurality of pixels each including aphotoelectric conversion element;

a column amplifier unit that obtains a difference between a resetcomponent and a signal component input from each pixel of the pixelarray unit via a signal line, and outputs the difference as a pixelsignal;

a capacitance unit that holds the pixel signal input from the columnamplifier unit; and

a successive approximation register analog-to-digital conversion unitthat converts an analog pixel signal input from the capacitance unitinto a digital signal, in which

the capacitance unit differentiates a single-phase pixel signal inputfrom the column amplifier unit using a reference voltage that defines azero voltage of the pixel signal.

[A-02] The imaging device according to [A-01] described above, in which

the column amplifier unit includes:

an amplifier to a non-inverting input terminal of which a potential ofthe signal line is input;

a first switch one end of which is connected to an output terminal ofthe amplifier and another end of which is connected to an invertinginput terminal of the amplifier;

a second switch one end of which is connected to the output terminal ofthe amplifier;

a first capacitance element one end of which is connected to another endof the second switch and another end of which is connected to theanother end of the first switch and the inverting input terminal of theamplifier;

a second capacitance element connected between the another end of thefirst capacitance element and the inverting input terminal of theamplifier, and a reference potential node; and

a third switch one end of which is connected to the another end of thesecond switch and one end of the first capacitance element, the thirdswitch to another end of which the reference voltage is applied.

[A-03] The imaging device according to [A-02] described above, in which

the column amplifier unit

puts the first switch into a closed state and charges the firstcapacitance element and the second capacitance element with the resetcomponent when the reset component is input, and puts the third switchinto a closed state and applies the reference voltage to the another endof the second switch and the one end of the first capacitance element,

then, puts the first switch and the third switch into an opened stateand puts the second switch into a closed state, and forms anon-inverting amplification circuit using the first capacitance element,the second capacitance element, and the amplifier, and

feeds back so that a voltage of a common connection node of the firstcapacitance element and the second capacitance element becomes a samevoltage as the signal component when the signal component is input.

[A-04] The imaging device according to [A-02] or [A-03] described above,in which

the capacitance unit

has a configuration of a differential circuit including a positive-sidecapacitance element charged with the pixel signal input from the columnamplifier unit, and a negative-side capacitance element charged with thereference voltage, and

includes a fourth switch that selectively short-circuits input ends ofthe positive-side capacitance element and the negative-side capacitanceelement.

[A-05] The imaging device according to [A-04] described above, in which

the fourth switch short-circuits the input ends of the positive-sidecapacitance element and the negative-side capacitance element when thepixel signal with which the positive-side capacitance element is chargedand the reference voltage with which the negative-side capacitanceelement is charged are transmitted to the successive approximationregister analog-to-digital conversion unit.

[A-06] The imaging device according to [A-05] described above, in which

the capacitance unit holds the pixel signal input from the columnamplifier unit by sampling by a switched capacitor.

[A-07] The imaging device according to any one of [A-01] to [A-06]described above, that

multiplexes and processes each potential of a plurality of signal linesvia a plurality of the column amplifier units and the capacitance unitscorresponding to the plurality of signal lines for one successiveapproximation register analog-to-digital converter of the successiveapproximation register analog-to-digital conversion unit.

[A-08] The imaging device according to [A-02] described above, in which

the capacitance unit is provided with:

a first node to which the pixel signal input from the column amplifierunit is supplied;

a second node to which the reference voltage is supplied;

a positive-side capacitance element and a negative-side capacitanceelement connected in series between the first node and the second node;

a fourth switch that selectively short-circuits the first node and thesecond node;

a fifth switch that selectively applies a common mode reference voltageof the successive approximation register analog-to-digital conversionunit to a common connection node of the positive-side capacitanceelement and the negative-side capacitance element;

a sixth switch that selectively connects the second node and a firstinput end of the successive approximation register analog-to-digitalconversion unit; and

a seventh switch that selectively connects the first node and a secondinput end of the successive approximation register analog-to-digitalconversion unit.

[A-09] The imaging device according to [A-08] described above, in which

the fourth switch is temporarily put into a closed state immediatelybefore the capacitance unit starts holding the pixel signal, andshort-circuits input ends of the positive-side capacitance element andthe negative-side capacitance element, and

the fifth switch is temporarily put into a closed state immediatelybefore the capacitance unit starts holding the pixel signal and in aperiod in which the pixel signal held by the capacitance unit istransferred to the successive approximation register analog-to-digitalconversion unit, and applies the common mode reference voltage of thesuccessive approximation register analog-to-digital conversion unit tothe common connection node of the positive-side capacitance element andthe negative-side capacitance element.

[A-10] The imaging device according to [A-02] described above, in which

the capacitance unit is provided with:

a first node to which the pixel signal input from the column amplifierunit is supplied;

a second node to which the reference voltage is supplied;

a positive-side capacitance element and a negative-side capacitanceelement connectable in series between the first node and the secondnode;

a 4a switch and a 4b switch connected in series between the first nodeand the second node;

a 5a switch, the positive-side capacitance element, the negative-sidecapacitance element, and a 5b switch connected in series between thefirst node and the second node;

a 5c switch that selectively applies a common mode reference voltage ofthe successive approximation register analog-to-digital conversion unitto a common connection node of the positive-side capacitance element andthe negative-side capacitance element;

a sixth switch that selectively connects the second node and a firstinput end of the successive approximation register analog-to-digitalconversion unit; and

a seventh switch that selectively connects the first node and a secondinput end of the successive approximation register analog-to-digitalconversion unit.

[A-11] The imaging device according to [A-10] described above, in which

the 4a switch and the 4b switch are temporarily put into a closed stateimmediately before the capacitance unit starts holding the pixel signaland immediately before the pixel signal held by the capacitance unit istransferred to the successive approximation register analog-to-digitalconversion unit, and apply the common mode reference voltage of thesuccessive approximation register analog-to-digital conversion unit tothe first node and the second node,

the 5a switch and the 5b switch are temporarily put into an opened stateimmediately before the pixel signal held by the capacitance unit istransferred to the successive approximation register analog-to-digitalconversion unit, and block the connection between the first node and thepositive-side capacitance element and block the connection between thesecond node and the negative-side capacitance element, and

the 5c switch is temporarily put into a closed state immediately beforethe capacitance unit starts holding the pixel signal and in a period inwhich the pixel signal held by the capacitance unit is transferred tothe successive approximation register analog-to-digital conversion unit,and applies the common mode reference voltage of the successiveapproximation register analog-to-digital conversion unit to the commonconnection node of the positive-side capacitance element and thenegative-side capacitance element.

[A-12] The imaging device according to [A-02] described above, in which

the capacitance unit is provided with:

a first node to which the pixel signal input from the column amplifierunit is supplied;

a second node to which the reference voltage is supplied;

a 4a switch and a 4b switch connected in series between the first nodeand the second node;

a positive-side capacitance element, a 5a switch, a 5b switch, and anegative-side capacitance element connected in series between the firstnode and the second node;

a 5c switch that selectively applies a common mode reference voltage ofthe successive approximation register analog-to-digital conversion unitto a common connection node of the 5a switch and the 5b switch;

a sixth switch that selectively connects the second node and a firstinput end of the successive approximation register analog-to-digitalconversion unit; and

a seventh switch that selectively connects the first node and a secondinput end of the successive approximation register analog-to-digitalconversion unit.

[A-13] The imaging device according to [A-12] described above, in which

the 4a switch and the 4b switch are temporarily put into a closed stateimmediately before the capacitance unit starts holding the pixel signaland immediately before the pixel signal held by the capacitance unit istransferred to the successive approximation register analog-to-digitalconversion unit, and apply the common mode reference voltage of thesuccessive approximation register analog-to-digital conversion unit tothe first node and the second node,

the 5c switch is temporarily put into a closed state immediately beforethe capacitance unit starts holding the pixel signal and in a period inwhich the pixel signal held by the capacitance unit is transferred tothe successive approximation register analog-to-digital conversion unit,and applies the common mode reference voltage of the successiveapproximation register analog-to-digital conversion unit to a commonconnection node of the positive-side capacitance element and thenegative-side capacitance element, and

the 5a switch and the 5b switch are temporarily put into an opened stateimmediately before the pixel signal held by the capacitance unit istransferred to the successive approximation register analog-to-digitalconversion unit, and block the connection between the positive-sidecapacitance element and the negative-side capacitance element.

[A-14] The imaging device according to [A-02] described above, in which

the capacitance unit is provided with:

a first node to which the pixel signal input from the column amplifierunit is supplied;

a second node to which the reference voltage is supplied;

a positive-side capacitance element one end of which is connected to thefirst node;

a third node to which another end of the positive-side capacitanceelement is connected;

a negative-side capacitance element one end of which is connected to thesecond node;

a fourth node to which another end of the negative-side capacitanceelement is connected;

a 4a switch and a 4b switch connected in series between the first nodeand the second node;

a 4c switch connected between the first node and the second node;

a 5a switch connected between the third node and the fourth node;

a 5b switch and a 5c switch connected in series between the third nodeand the fourth node;

a sixth switch that selectively connects the third node and a firstinput end of the successive approximation register analog-to-digitalconversion unit; and

a seventh switch that selectively connects the fourth node and a secondinput end of the successive approximation register analog-to-digitalconversion unit.

[A-15] The imaging device according to [A-14] described above, in which

the 4a switch and the 4b switch are temporarily put into a closed statein a period in which the pixel signal held by the capacitance unit istransferred to the successive approximation register analog-to-digitalconversion unit, and apply a common mode reference voltage of thesuccessive approximation register analog-to-digital conversion unit tothe first node and the second node,

the 4c switch is put into a closed state immediately before thecapacitance unit starts holding the pixel signal, and short-circuits thefirst node and the second node,

the 5a switch short-circuits the third node and the fourth node in aperiod in which the capacitance unit holds the pixel signal, and

the 5b switch and the 5c switch are put into a closed state immediatelybefore the capacitance unit starts holding the pixel signal, and applythe reference voltage to the third node and the fourth node.

[A-16] The imaging device according to [A-02] described above, in which

the capacitance unit is provided with:

a first node to which the pixel signal input from the column amplifierunit is supplied;

a second node to which the reference voltage is supplied;

a positive-side capacitance element one end of which is connected to thefirst node;

a third node to which another end of the positive-side capacitanceelement is connected;

a negative-side capacitance element one end of which is connected to thesecond node;

a fourth node to which another end of the negative-side capacitanceelement is connected;

a fourth switch connected between the first node and the second node;

a 5a switch and a 5b switch connected in series between the third nodeand the fourth node;

a 5c switch that selectively applies a common mode reference voltage ofthe successive approximation register analog-to-digital conversion unitto a common connection node of the 5a switch and the 5b switch;

a sixth switch that selectively connects the third node and a firstinput end of the successive approximation register analog-to-digitalconversion unit; and

a seventh switch that selectively connects the fourth node and a secondinput end of the successive approximation register analog-to-digitalconversion unit.

[A-17] The imaging device according to [A-16] described above, in which

the fourth switch is put into a closed state immediately before thecapacitance unit starts holding the pixel signal and in a period inwhich the pixel signal held by the capacitance unit is transferred tothe successive approximation register analog-to-digital conversion unit,and short-circuits the first node and the second node,

the 5a switch and the 5b switch are put into a closed state immediatelybefore a period in which the capacitance unit holds the pixel signaluntil the holding period ends, and short-circuit the third node and thefourth node; and

the 5c switch is put into a closed state immediately before thecapacitance unit starts holding the pixel signal, and selectivelyapplies the common mode reference voltage of the successiveapproximation register analog-to-digital conversion unit to the commonconnection node of the 5a switch and the 5b switch.

[A-18] The imaging device according to [A-02] described above, in which

the capacitance unit is provided with:

a first node to which the pixel signal input from the column amplifierunit is supplied;

a second node to which the reference voltage is supplied;

a positive-side capacitance element one end of which is connected to thefirst node;

a third node to which another end of the positive-side capacitanceelement is connected;

a negative-side capacitance element one end of which is connected to thesecond node;

a fourth node to which another end of the negative-side capacitanceelement is connected;

a 4a switch and a 4b switch connected in series between the first nodeand the second node;

a 4c switch that selectively applies the reference voltage to a commonconnection node of the 4a switch and the 4b switch;

a 5a switch and a 5b switch connected in series between the third nodeand the fourth node;

a 5c switch that selectively applies a common mode reference voltage ofthe successive approximation register analog-to-digital conversion unitto a common connection node of the 5a switch and the 5b switch;

a sixth switch that selectively connects the third node and a firstinput end of the successive approximation register analog-to-digitalconversion unit; and

a seventh switch that selectively connects the fourth node and a secondinput end of the successive approximation register analog-to-digitalconversion unit.

[A-19] The imaging device according to [A-18] described above, in which

the 4a switch and the 4b switch are temporarily put into a closed stateimmediately before the capacitance unit starts holding the pixel signal,immediately before a period in which the pixel signal held by thecapacitance unit is transferred to the successive approximation registeranalog-to-digital conversion unit, and the transferring period, andshort-circuit the first node and the second node,

the 4c switch is temporarily put into a closed state immediately beforethe capacitance unit starts holding the pixel signal and immediatelybefore a period in which the pixel signal held by the capacitance unitis transferred to the successive approximation registeranalog-to-digital conversion unit, and applies the reference voltage tothe common connection node of the 4a switch and the 4b switch,

the 5a switch and the 5b switch are temporarily put into a closed stateimmediately before the capacitance unit starts holding the pixel signaland in a period in which the capacitance unit holds the pixel signal,and short-circuit the third node and the fourth node, and

the 5c switch is temporarily put into a closed state immediately beforethe capacitance unit starts holding the pixel signal, and applies thecommon mode reference voltage of the successive approximation registeranalog-to-digital conversion unit to the common connection node of the5a switch and the 5b switch.

<<B. Electronic Device>>

[B-01] An electronic device provided with:

an imaging device that outputs a photoelectrically converted digitalsignal; and

a signal processing unit that performs signal processing on the basis ofthe digital signal, in which

the imaging device is provided with:

a pixel array unit including a plurality of pixels each including aphotoelectric conversion element;

a column amplifier unit that obtains a difference between a resetcomponent and a signal component input from each pixel of the pixelarray unit via a signal line, and outputs the difference as a pixelsignal;

a capacitance unit that holds the pixel signal input from the columnamplifier unit; and

a successive approximation register analog-to-digital conversion unitthat converts an analog signal input from the capacitance unit into adigital signal, and

the capacitance unit differentiates a single-phase pixel signal inputfrom the column amplifier unit using a reference voltage that defines azero voltage of the pixel signal.

[B-02] The electronic device according to [B-01] described above, inwhich

the column amplifier unit includes:

an amplifier to a non-inverting input terminal of which a potential ofthe signal line is input;

a first switch one end of which is connected to an output terminal ofthe amplifier and another end of which is connected to an invertinginput terminal of the amplifier;

a second switch one end of which is connected to the output terminal ofthe amplifier;

a first capacitance element one end of which is connected to another endof the second switch and another end of which is connected to theanother end of the first switch and the inverting input terminal of theamplifier;

a second capacitance element connected between the another end of thefirst capacitance element and the inverting input terminal of theamplifier, and a reference potential node; and

a third switch one end of which is connected to the another end of thesecond switch and one end of the first capacitance element, the thirdswitch to another end of which the reference voltage is applied.

[B-03] The electronic device according [B-02] described above, in which

the column amplifier unit

puts the first switch into a closed state and charges the firstcapacitance element and the second capacitance element with the resetcomponent when the reset component is input, and puts the third switchinto a closed state and applies the reference voltage to the another endof the second switch and the one end of the first capacitance element,

then, puts the first switch and the third switch into an opened stateand puts the second switch into a closed state, and forms anon-inverting amplification circuit using the first capacitance element,the second capacitance element, and the amplifier, and

feeds back so that a voltage of a common connection node of the firstcapacitance element and the second capacitance element becomes a samevoltage as the signal component when the signal component is input.

[B-04] The electronic device according to [B-02] or [B-03] describedabove, in which

the capacitance unit

has a configuration of a differential circuit including a positive-sidecapacitance element charged with the pixel signal input from the columnamplifier unit, and a negative-side capacitance element charged with thereference voltage, and

includes a fourth switch that selectively short-circuits input ends ofthe positive-side capacitance element and the negative-side capacitanceelement.

[B-05] The electronic device according to [B-04] described above, inwhich

the fourth switch short-circuits the input ends of the positive-sidecapacitance element and the negative-side capacitance element when thepixel signal with which the positive-side capacitance element is chargedand the reference voltage with which the negative-side capacitanceelement is charged are transmitted to the successive approximationregister analog-to-digital conversion unit.

[B-06] The electronic device according to [B-05] described above, inwhich

the capacitance unit holds the pixel signal input from the columnamplifier unit by sampling by a switched capacitor.

[B-07] The electronic device according to any one of [B-01] to [B-06]described above, that

multiplexes and processes each potential of a plurality of signal linesvia a plurality of the column amplifier units and the capacitance unitscorresponding to the plurality of signal lines for one successiveapproximation register analog-to-digital converter of the successiveapproximation register analog-to-digital conversion unit.

REFERENCE SIGNS LIST

-   10 CMOS image sensor-   11 Pixel array unit-   12 Row selection unit-   13 Constant current source unit-   14 Column amplifier unit-   15 Analog-to-digital conversion unit-   15A Successive approximation register analog-to-digital conversion    unit-   16 Horizontal transfer scanning unit-   17 Signal processing unit-   18 Timing control unit-   19 Capacitance unit-   20 Pixel (pixel circuit)-   21 Photodiode (photoelectric conversion element)-   22 Transfer transistor-   23 Reset transistor-   24 Amplification transistor-   25 Selection transistor-   31 (31 ₁ to 31 _(m)) Pixel control line-   32 (32 ₁ to 32 _(n)) Signal line-   50 Indirect TOF distance image sensor-   60 Light source-   100 Imaging system-   140 Column amplifier-   150 Successive approximation register analog-to-digital converter-   160 Reference voltage generation unit-   190 Capacitance demultiplexer-   1400 Current reuse column amplifier (CRCA)-   VR Reference voltage-   V_(CM) Output common mode reference voltage

1. An imaging device comprising: a pixel array unit including aplurality of pixels each including a photoelectric conversion element; acolumn amplifier unit that obtains a difference between a resetcomponent and a signal component input from each pixel of the pixelarray unit via a signal line, and outputs the difference as a pixelsignal; a capacitance unit that holds the pixel signal input from thecolumn amplifier unit; and a successive approximation registeranalog-to-digital conversion unit that converts an analog pixel signalinput from the capacitance unit into a digital signal, wherein thecapacitance unit differentiates a single-phase pixel signal input fromthe column amplifier unit using a reference voltage that defines a zerovoltage of the pixel signal.
 2. The imaging device according to claim 1,wherein the column amplifier unit includes: an amplifier to anon-inverting input terminal of which a potential of the signal line isinput; a first switch one end of which is connected to an outputterminal of the amplifier and another end of which is connected to aninverting input terminal of the amplifier; a second switch one end ofwhich is connected to the output terminal of the amplifier; a firstcapacitance element one end of which is connected to another end of thesecond switch and another end of which is connected to the another endof the first switch and the inverting input terminal of the amplifier; asecond capacitance element connected between the another end of thefirst capacitance element and the inverting input terminal of theamplifier, and a reference potential node; and a third switch one end ofwhich is connected to the another end of the second switch and one endof the first capacitance element, the third switch to another end ofwhich the reference voltage is applied.
 3. The imaging device accordingto claim 2, wherein the column amplifier unit puts the first switch intoa closed state and charges the first capacitance element and the secondcapacitance element with the reset component when the reset component isinput, and puts the third switch into a closed state and applies thereference voltage to the another end of the second switch and the oneend of the first capacitance element, then, puts the first switch andthe third switch into an opened state and puts the second switch into aclosed state, and forms a non-inverting amplification circuit using thefirst capacitance element, the second capacitance element, and theamplifier, and feeds back so that a voltage of a common connection nodeof the first capacitance element and the second capacitance elementbecomes a same voltage as the signal component when the signal componentis input.
 4. The imaging device according to claim 2, wherein thecapacitance unit has a configuration of a differential circuit includinga positive-side capacitance element charged with the pixel signal inputfrom the column amplifier unit, and a negative-side capacitance elementcharged with the reference voltage, and includes a fourth switch thatselectively short-circuits input ends of the positive-side capacitanceelement and the negative-side capacitance element.
 5. The imaging deviceaccording to claim 4, wherein the fourth switch short-circuits the inputends of the positive-side capacitance element and the negative-sidecapacitance element when the pixel signal with which the positive-sidecapacitance element is charged and the reference voltage with which thenegative-side capacitance element is charged are transmitted to thesuccessive approximation register analog-to-digital conversion unit. 6.The imaging device according to claim 5, wherein the capacitance unitholds the pixel signal input from the column amplifier unit by samplingby a switched capacitor.
 7. The imaging device according to claim 1,that multiplexes and processes each potential of a plurality of signallines via a plurality of the column amplifier units and the capacitanceunits corresponding to the plurality of signal lines for one successiveapproximation register analog-to-digital converter of the successiveapproximation register analog-to-digital conversion unit.
 8. The imagingdevice according to claim 2, wherein the capacitance unit is providedwith: a first node to which the pixel signal input from the columnamplifier unit is supplied; a second node to which the reference voltageis supplied; a positive-side capacitance element and a negative-sidecapacitance element connected in series between the first node and thesecond node; a fourth switch that selectively short-circuits the firstnode and the second node; a fifth switch that selectively applies acommon mode reference voltage of the successive approximation registeranalog-to-digital conversion unit to a common connection node of thepositive-side capacitance element and the negative-side capacitanceelement; a sixth switch that selectively connects the second node and afirst input end of the successive approximation registeranalog-to-digital conversion unit; and a seventh switch that selectivelyconnects the first node and a second input end of the successiveapproximation register analog-to-digital conversion unit.
 9. The imagingdevice according to claim 8, wherein the fourth switch is temporarilyput into a closed state immediately before the capacitance unit startsholding the pixel signal, and short-circuits input ends of thepositive-side capacitance element and the negative-side capacitanceelement, and the fifth switch is temporarily put into a closed stateimmediately before the capacitance unit starts holding the pixel signaland in a period in which the pixel signal held by the capacitance unitis transferred to the successive approximation registeranalog-to-digital conversion unit, and applies the common mode referencevoltage of the successive approximation register analog-to-digitalconversion unit to the common connection node of the positive-sidecapacitance element and the negative-side capacitance element.
 10. Theimaging device according to claim 2, wherein the capacitance unit isprovided with: a first node to which the pixel signal input from thecolumn amplifier unit is supplied; a second node to which the referencevoltage is supplied; a positive-side capacitance element and anegative-side capacitance element connectable in series between thefirst node and the second node; a 4a switch and a 4b switch connected inseries between the first node and the second node; a 5a switch, thepositive-side capacitance element, the negative-side capacitanceelement, and a 5b switch connected in series between the first node andthe second node; a 5c switch that selectively applies a common modereference voltage of the successive approximation registeranalog-to-digital conversion unit to a common connection node of thepositive-side capacitance element and the negative-side capacitanceelement; a sixth switch that selectively connects the second node and afirst input end of the successive approximation registeranalog-to-digital conversion unit; and a seventh switch that selectivelyconnects the first node and a second input end of the successiveapproximation register analog-to-digital conversion unit.
 11. Theimaging device according to claim 10, wherein the 4a switch and the 4bswitch are temporarily put into a closed state immediately before thecapacitance unit starts holding the pixel signal and immediately beforethe pixel signal held by the capacitance unit is transferred to thesuccessive approximation register analog-to-digital conversion unit, andapply the common mode reference voltage of the successive approximationregister analog-to-digital conversion unit to the first node and thesecond node, the 5a switch and the 5b switch are temporarily put into anopened state immediately before the pixel signal held by the capacitanceunit is transferred to the successive approximation registeranalog-to-digital conversion unit, and block the connection between thefirst node and the positive-side capacitance element and block theconnection between the second node and the negative-side capacitanceelement, and the 5c switch is temporarily put into a closed stateimmediately before the capacitance unit starts holding the pixel signaland in a period in which the pixel signal held by the capacitance unitis transferred to the successive approximation registeranalog-to-digital conversion unit, and applies the common mode referencevoltage of the successive approximation register analog-to-digitalconversion unit to the common connection node of the positive-sidecapacitance element and the negative-side capacitance element.
 12. Theimaging device according to claim 2, wherein the capacitance unit isprovided with: a first node to which the pixel signal input from thecolumn amplifier unit is supplied; a second node to which the referencevoltage is supplied; a 4a switch and a 4b switch connected in seriesbetween the first node and the second node; a positive-side capacitanceelement, a 5a switch, a 5b switch, and a negative-side capacitanceelement connected in series between the first node and the second node;a 5c switch that selectively applies a common mode reference voltage ofthe successive approximation register analog-to-digital conversion unitto a common connection node of the 5a switch and the 5b switch; a sixthswitch that selectively connects the second node and a first input endof the successive approximation register analog-to-digital conversionunit; and a seventh switch that selectively connects the first node anda second input end of the successive approximation registeranalog-to-digital conversion unit.
 13. The imaging device according toclaim 12, wherein the 4a switch and the 4b switch are temporarily putinto a closed state immediately before the capacitance unit startsholding the pixel signal and immediately before the pixel signal held bythe capacitance unit is transferred to the successive approximationregister analog-to-digital conversion unit, and apply the common modereference voltage of the successive approximation registeranalog-to-digital conversion unit to the first node and the second node,the 5c switch is temporarily put into a closed state immediately beforethe capacitance unit starts holding the pixel signal and in a period inwhich the pixel signal held by the capacitance unit is transferred tothe successive approximation register analog-to-digital conversion unit,and applies the common mode reference voltage of the successiveapproximation register analog-to-digital conversion unit to a commonconnection node of the positive-side capacitance element and thenegative-side capacitance element, and the 5a switch and the 5b switchare temporarily put into an opened state immediately before the pixelsignal held by the capacitance unit is transferred to the successiveapproximation register analog-to-digital conversion unit, and block theconnection between the positive-side capacitance element and thenegative-side capacitance element.
 14. The imaging device according toclaim 2, wherein the capacitance unit is provided with: a first node towhich the pixel signal input from the column amplifier unit is supplied;a second node to which the reference voltage is supplied; apositive-side capacitance element one end of which is connected to thefirst node; a third node to which another end of the positive-sidecapacitance element is connected; a negative-side capacitance elementone end of which is connected to the second node; a fourth node to whichanother end of the negative-side capacitance element is connected; a 4aswitch and a 4b switch connected in series between the first node andthe second node; a 4c switch connected between the first node and thesecond node; a 5a switch connected between the third node and the fourthnode; a 5b switch and a 5c switch connected in series between the thirdnode and the fourth node; a sixth switch that selectively connects thethird node and a first input end of the successive approximationregister analog-to-digital conversion unit; and a seventh switch thatselectively connects the fourth node and a second input end of thesuccessive approximation register analog-to-digital conversion unit. 15.The imaging device according to claim 14, wherein the 4a switch and the4b switch are temporarily put into a closed state in a period in whichthe pixel signal held by the capacitance unit is transferred to thesuccessive approximation register analog-to-digital conversion unit, andapply a common mode reference voltage of the successive approximationregister analog-to-digital conversion unit to the first node and thesecond node, the 4c switch is put into a closed state immediately beforethe capacitance unit starts holding the pixel signal, and short-circuitsthe first node and the second node, the 5a switch short-circuits thethird node and the fourth node in a period in which the capacitance unitholds the pixel signal, and the 5b switch and the 5c switch are put intoa closed state immediately before the capacitance unit starts holdingthe pixel signal, and apply the reference voltage to the third node andthe fourth node.
 16. The imaging device according to claim 2, whereinthe capacitance unit is provided with: a first node to which the pixelsignal input from the column amplifier unit is supplied; a second nodeto which the reference voltage is supplied; a positive-side capacitanceelement one end of which is connected to the first node; a third node towhich another end of the positive-side capacitance element is connected;a negative-side capacitance element one end of which is connected to thesecond node; a fourth node to which another end of the negative-sidecapacitance element is connected; a fourth switch connected between thefirst node and the second node; a 5a switch and a 5b switch connected inseries between the third node and the fourth node; a 5c switch thatselectively applies a common mode reference voltage of the successiveapproximation register analog-to-digital conversion unit to a commonconnection node of the 5a switch and the 5b switch; a sixth switch thatselectively connects the third node and a first input end of thesuccessive approximation register analog-to-digital conversion unit; anda seventh switch that selectively connects the fourth node and a secondinput end of the successive approximation register analog-to-digitalconversion unit.
 17. The imaging device according to claim 16, whereinthe fourth switch is put into a closed state immediately before thecapacitance unit starts holding the pixel signal and in a period inwhich the pixel signal held by the capacitance unit is transferred tothe successive approximation register analog-to-digital conversion unit,and short-circuits the first node and the second node, the 5a switch andthe 5b switch are put into a closed state immediately before a period inwhich the capacitance unit holds the pixel signal until the holdingperiod ends, and short-circuit the third node and the fourth node; andthe 5c switch is put into a closed state immediately before thecapacitance unit starts holding the pixel signal, and selectivelyapplies the common mode reference voltage of the successiveapproximation register analog-to-digital conversion unit to the commonconnection node of the 5a switch and the 5b switch.
 18. The imagingdevice according to claim 2, wherein the capacitance unit is providedwith: a first node to which the pixel signal input from the columnamplifier unit is supplied; a second node to which the reference voltageis supplied; a positive-side capacitance element one end of which isconnected to the first node; a third node to which another end of thepositive-side capacitance element is connected; a negative-sidecapacitance element one end of which is connected to the second node; afourth node to which another end of the negative-side capacitanceelement is connected; a 4a switch and a 4b switch connected in seriesbetween the first node and the second node; a 4c switch that selectivelyapplies the reference voltage to a common connection node of the 4aswitch and the 4b switch; a 5a switch and a 5b switch connected inseries between the third node and the fourth node; a 5c switch thatselectively applies a common mode reference voltage of the successiveapproximation register analog-to-digital conversion unit to a commonconnection node of the 5a switch and the 5b switch; a sixth switch thatselectively connects the third node and a first input end of thesuccessive approximation register analog-to-digital conversion unit; anda seventh switch that selectively connects the fourth node and a secondinput end of the successive approximation register analog-to-digitalconversion unit.
 19. The imaging device according to claim 18, whereinthe 4a switch and the 4b switch are temporarily put into a closed stateimmediately before the capacitance unit starts holding the pixel signal,immediately before a period in which the pixel signal held by thecapacitance unit is transferred to the successive approximation registeranalog-to-digital conversion unit, and the transferring period, andshort-circuit the first node and the second node, the 4c switch istemporarily put into a closed state immediately before the capacitanceunit starts holding the pixel signal and immediately before a period inwhich the pixel signal held by the capacitance unit is transferred tothe successive approximation register analog-to-digital conversion unit,and applies the reference voltage to the common connection node of the4a switch and the 4b switch, the 5a switch and the 5b switch aretemporarily put into a closed state immediately before the capacitanceunit starts holding the pixel signal and in a period in which thecapacitance unit holds the pixel signal, and short-circuit the thirdnode and the fourth node, and the 5c switch is temporarily put into aclosed state immediately before the capacitance unit starts holding thepixel signal, and applies the common mode reference voltage of thesuccessive approximation register analog-to-digital conversion unit tothe common connection node of the 5a switch and the 5b switch.
 20. Anelectronic device comprising: an imaging device that outputs aphotoelectrically converted digital signal; and a signal processing unitthat performs signal processing on a basis of the digital signal,wherein the imaging device is provided with: a pixel array unitincluding a plurality of pixels each including a photoelectricconversion element; a column amplifier unit that obtains a differencebetween a reset component and a signal component input from each pixelof the pixel array unit via a signal line, and outputs the difference asa pixel signal; a capacitance unit that holds the pixel signal inputfrom the column amplifier unit; and a successive approximation registeranalog-to-digital conversion unit that converts an analog signal inputfrom the capacitance unit into a digital signal, and the capacitanceunit differentiates a single-phase pixel signal input from the columnamplifier unit using a reference voltage that defines a zero voltage ofthe pixel signal.